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This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions. [ABSTRACT FROM AUTHOR]

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor's dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 Vp. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal's feasibility. [ABSTRACT FROM AUTHOR]

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analytical comparison of the single‐Miller capacitor frequency compensation techniques suitable for three‐stage complementary metal–oxide–semiconductor (CMOS) operational transconductance amplifiers (OTAs). The comparison is carried out with the aid of a figure of merit that expresses a trade‐off among gain‐bandwidth product, load capacitance, and total transconductance, for equal values of the phase margin. The results found can be used before the transistor‐level design step and provide useful guidelines for the optimization of the small‐signal performance. Simulations by using a 65‐nm standard CMOS technology confirming the effectiveness of the theoretical comparison for 10 different OTA topologies are also provided. [ABSTRACT FROM AUTHOR]

This paper describes a design procedure that optimises for noise and power dissipation of CMOS folded-cascode operational transconductance amplifier. The proposed design procedure is derived based on the unified EKV MOSFET equation and employs the inversion coefficient and transconductance efficiency of MOSFET as the essential design parameters. Key specifications of operational amplifier and CMOS process parameters are used with the proposed procedure to calculate the circuit parameters. A MATLAB routine is written to execute the design steps and MATLAB simulations are carried out to show how the circuit parameters are affected by the noise requirements. Finally, transistor-level circuit simulations are performed with 0.13 μ m CMOS process parameters to validate the efficacy of the proposed design procedure. [ABSTRACT FROM AUTHOR]

Advances over the last decades in electronic design automation (EDA) for the design of digital integrated circuits (ICs), have led to the development of a robust set of tools and methodologies that automate almost all low-level phases of the digital design workflow. In contrast, analog IC design remains a mostly handmade, time-consuming and knowledge-intensive process. The amount of design iterations can be heavily cut down by the use of realistic value tables through the $g_{m}/I_{D}$ design technique; however, the process still remains time-consuming and error-prone, with an end result of limited applicability beyond the scope of the initial specifications. The slice-based design methodology, first introduced in this paper, is a new approach to analog IC design, suitable for implementation in EDA tools, that aims to reduce the amount of time and expertise required from the user. This methodology, inspired by the $g_{m}/I_{D}$ design technique, is based on the use of pre-designed circuit cells, which can be connected in parallel to scale important performance metrics. Although not limited to any particular fabrication process, the present paper explores the application of the proposed design methodology to CMOS technologies, and in the context of a particular target application: low-noise charge-sensitive amplifiers (CSA) used for instrumentation in particle physics experiments. The methodology was successfully applied and validated through the design, fabrication and testing of a CSA with configurable noise performance.

A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. [ABSTRACT FROM AUTHOR]

An operational amplifier (OPAMP) for portable devices with dual supply voltage is presented in this work. The design is realized with a 600 mV supply for the core design and a 1.8 V supply for the biasing circuit to improve input common mode range (ICMR), gain, and common mode rejection ratio (CMRR). The designed amplifier is implemented with dynamic threshold voltage MOSFET (DTMOS) transistors to decrease power consumption and increase the performance of the design. The power consumption of the core design is obtained as 2 μ W while the biasing circuitry consumes 7.38 μ W. The application of different supply voltages has greatly increased the gain of the circuit, where the circuit exhibits 100.2 dB DC gain and 3.41 MHz gain bandwidth product (GBW). CMRR of the designed circuit is 84.22 dB. The simulations are performed in Cadence environment with 0.18 μ m CMOS technology. [ABSTRACT FROM AUTHOR]

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

High-performance single-transistor current source is crucial to analog design in advanced CMOS processes. Various approaches to enhance the output resistance of single-transistor current source are studied in this brief in the view of adaptive control. Then a novel compact implementation is proposed, and used to build a fully differential OTA with improved dc gain and common-mode rejection in a 55 nm CMOS with a supply of 1.1 V. [ABSTRACT FROM AUTHOR]

This brief presents a linearization method for the voltage-to-current (V-to-I) stage of voltage-controlled oscillators (VCOs). A floating-gate transistor is utilized at the VCO’s input stage as a low-overhead method for V-to-I linearization. The resulting VCO is a ring oscillator with an extended linear voltage-to-frequency range. The ring oscillator VCO (RO-VCO) has also been included in a VCO-based analog-to-digital converter (VCO-ADC) to showcase how the linearization technique can be leveraged to improve system performance. The measured results from the linearized RO-VCO are compared to current state-of-the-art designs, and the VCO-ADC is compared to a standard architecture. The circuits were fabricated in a standard $0.35~\mu \text{m}$ complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

An alternative procedure for the implementation of fractional-order compensators is presented in this work. The employment of a curve-fitting-based approximation technique for the approximation of the compensator transfer function offers improved accuracy compared to the Oustaloup and Padé methods. As a design example, a lead compensator intended for usage in car suspension systems is realized. The open-loop and closed-loop behavior of the system is evaluated by post-layout simulation results obtained using the Cadence IC design suite and the Metal Oxide Semiconductor (MOS) transistor models provided by the Austria Mikro Systeme 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The derived results verify the efficient performance of the introduced implementation. [ABSTRACT FROM AUTHOR]

Summary: This research reports the development of an RF sensor integrated circuit (IC) chip capable of tracking the directionality of RF remote emissions. The IC design uses an angle‐of‐arrival algorithm, and it is designed for the 180 nm CMOS technology and applicable to other technologies, also. The sensor chip requires two pairs of antennas aligned and placed at distance s for detection of azimuthal and polar angles of the RF incident wave. The circuit consists of custom designed low‐noise amplifiers (LNAs) at the front end, with a novel design of double‐balanced Gilbert cell mixers (GCMs). This amplifies and mixes the signals from the antennas and converts the phase difference Δφ into an equivalent output voltage map suitable for an 18‐bit analog to digital converter. Systematic optimization techniques were developed to maximize the third‐order intercept point and suppress flicker noise for the LNAs and GCMs, resulting in improved sensing accuracy. The overall system‐level evaluation results showed state‐of‐art angle‐of‐arrival sensing capability with an upper limit error of 3.447°. [ABSTRACT FROM AUTHOR]

A generalized structure that is capable of implementing power-law filters derived from 1st and 2nd-order mother filter functions is presented in this work. This is achieved thanks to the employment of Operational Transconductance Amplifiers (OTAs) as active elements, because of the electronic tuning capability of their transconductance parameter. Appropriate design examples are provided and the performance of the introduced structure is evaluated through simulation results using the Cadence Integrated Circuits (IC) design suite and Metal Oxide Semiconductor (MOS) transistors models available from the Austria Mikro Systeme (AMS) 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process.

In this article, a new CMOS voltage follower, with class AB output, derived by merging the super follower and the flipped voltage follower, is introduced. The resulting cell exhibits lower output impedance than its predecessors. Expressions for the behavior of the proposed follower are derived and verified by circuit simulations in Eldo using the C5N CMOS process models available through The MOSIS Service. The conducted analysis shows an improved performance of the presented circuit with respect to the flipped- and super followers. To prove the principle, a test cell was fabricated in the mentioned technology and characterized. Measurement results show quasi-symmetric rising and falling edges and a gain–bandwidth product of 32 MHz with a load capacitance of 47 pF. The power consumption of the cell is $138~\mu \text{W}$ with 2-V supply. Résumé—Dans cet article, un nouveau suiveur de tension CMOS, avec une sortie de classe AB, dérivé de la fusion du super suiveur et du suiveur de tension inversé, est présenté. La cellule résultante présente une impédance de sortie inférieure à celle de ses prédécesseurs. Les expressions pour le comportement du suiveur proposé sont dérivées et vérifiées par des simulations de circuits dans Eldo en utilisant les modèles de processus CMOS C5N disponibles via le service MOSIS. L’analyse effectuée montre une amélioration des performances du circuit présenté par rapport aux suiveurs super et inversé. Pour prouver le principe, une cellule d’essai a été fabriquée dans la technologie mentionnée et caractérisée. Les résultats de mesure montrent des fronts montants et descendants quasi-symétriques et un produit gain-largeur de bande de 32 MHz avec une capacité de charge de 47 pF. La consommation en puissance electrique de la cellule est de 138 $\mu$ W avec une alimentation 2 V. [ABSTRACT FROM AUTHOR]

The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One shortcoming of state-of-the-art ET PAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma–Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W. [ABSTRACT FROM AUTHOR]

This paper introduces a fractional-order eardrum Type-II model, which is derived using fractional calculus to reduce the number of elements compared to its integer-order counterpart. The proposed fractional-order model parameters are extracted and compared using five meta-heuristic optimization techniques. The CMOS implementation of the model is performed using the Design Kit of the Austria Mikro Systeme (AMS) 0.35 μ m CMOS process, while the simulations have been performed using the Cadence IC design suite. [ABSTRACT FROM AUTHOR]

Two 4-bit active phase shifters integrated with all digital control circuitry in 0.13-mu m RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter for quadrature signaling with minimum loss and wide operation bandwidth. Both phase shifters can change phases with less than about 2 dB of RMS amplitude imbalance for all phase states through an associated DAC control. For the X- and Ku-band phase shifter, the RMS phase error is less than 10 degrees over the entire 5-18 GHz range. The average insertion loss ranges from -3 dB; to -0.2 dB at 5-20 GHz. The input P-1dB for all 4-bit phase states is typically - 5.4 +/- 1.3 dBm at 12 GHz in the X- and.Ku-band phase shifter. The K-band phase shifter exhibits 6.5-13 degrees of RMS phase error at 15-26 GHz. The average insertion loss is from -4.6 to -3 dB at 15-26 GHz. The input P-1dB of the K-band phase shifter is -0.8 +/- 1.1 dBm at 24 GHz. For both phase shifters, the core size excluding all the pads and the output 50 Omega matching circuits, inserted for measurement purpose only, is very small, 0.33 x 0.43 mm(2). The total current consumption is 5.8 mA in the X- and Ku-band phase shifter and 7.8 mA in the K-band phase shifter, from a 1.5 V supply voltage.

The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-mu m CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

An alternative procedure for the implementation of fractional-order compensators is presented in this work. The employment of a curve-fitting-based approximation technique for the approximation of the compensator transfer function offers improved accuracy compared to the Oustaloup and Padé methods. As a design example, a lead compensator intended for usage in car suspension systems is realized. The open-loop and closed-loop behavior of the system is evaluated by post-layout simulation results obtained using the Cadence IC design suite and the Metal Oxide Semiconductor (MOS) transistor models provided by the Austria Mikro Systeme 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process. The derived results verify the efficient performance of the introduced implementation.

Fractional-order controllers have gained significant research interest in various practical applications due to the additional degrees of freedom offered in their tuning process. The main contribution of this work is the analog implementation, for the first time in the literature, of a fractional-order controller with a transfer function that is not directly constructed from terms of the fractional-order Laplacian operator. This is achieved using Padé approximation, and the resulting integer-order transfer function is implemented using operational transconductance amplifiers as active elements. Post-layout simulation results verify the validity of the introduced procedure.

High-throughput recordings of small current are becoming more common in biosensor applications, including in vivo dopamine measurements, single-cell electrophysiology, photoplethysmography, pulse oximetry, and nanopore recordings. Thus, a highly scalable transimpedance amplifier design is in demand. Half-shared amplifier design is one way to improve the scalability by sharing the non-inverting side of the operational amplifier design for many inverting halves. This method reduces silicon area and power by nearly half compared to using independent operational amplifiers. In this paper, we analyze the scalability of a simple half-shared amplifier structure while investigating the tradeoff of increasing the number of inverting half amplifiers sharing a single non-inverting half. A transimpedance amplifier is designed using the half-shared structure to minimize the size per amplifier. The transimpedance amplifier is based on a current integration of a capacitor. The noise analysis of the integration amplifier is a challenging task because it does not reach a steady-state, thus, being a non-stationary circuit. For frequency analysis, a conversion method is discussed to estimate the noise characteristic in the simulation. The array design of 1024 transimpedance amplifiers is fabricated using a standard 0.35 μm process and is tested to confirm the validity of above analysis. The amplifier array exhibits high linearity in transimpedance gain (7.00 mV/pA for high gain and 0.86 mV/pA for low gain), low mismatch of 1.65 mV across the entire 1024 amplifier array, and extremely low noise. The technique will be crucial in enabling the fabrication of larger arrays to enable higher throughput measurement tools for biosensor applications. [ABSTRACT FROM AUTHOR]

The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS transistors in OTAs are biased in the weak inversion region, the power dissipation and the dc bias voltage of operation are also minimized. In addition, the partial fraction expansion tool has been utilized, in order to achieve reduction of the spread of the required time-constants and scaling factors. The performance of the proposed scheme has been evaluated, at post-layout level, using MOS transistors models provided by the 0.35 μ m Austria Mikro Systeme technology CMOS process, and the Cadence IC design suite.

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to −39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment.

We describe a supply modulator comprising a proposed delay-based hysteresis controller, proposed wideband class-AB amplifier, and class-D amplifier for an envelope tracking (ET) power amplifier (PA). We investigate the power dissipation and optimization method of the supply modulator for wideband applications taking into consideration the propagation delay, and show that a controller with zero threshold current not only improves the bandwidth of the supply modulator but also reduces its power dissipation. Based on our investigations, we propose a delay-based hysteresis controller embodying a novel high-speed current comparator whose reference current (threshold current) is zero, thereby achieving higher power-efficiency and simpler hardware. We further propose a class-AB amplifier, which features a high bandwidth and accurately controlled quiescent current. The proposed supply modulator features simultaneously the wide bandwidth (40 MHz), high output power (2.5 W), high peak efficiency (91%), high output voltage swing (3 V), and low output ripple noise (4 mVrms) at 3.6-V supply. The ET PA embodying our proposed supply modulator achieves a high power-efficiency of 41.4% at 28.5-dBm peak output power and 34.4% at 3-dB backoff—a significant >1.6× improvement over the radio frequency PA without the supply modulator. [ABSTRACT FROM AUTHOR]

A voltage-controlled current amplifier/attenuator in a standard 0.35- ${\mu }\text{m}$ CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm2. A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 ${\mu }\text{W}$ with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator. [ABSTRACT FROM AUTHOR]

The approximations of fractional-order differentiator/integrator transfer functions are currently performed using integer-order rational functions, which are in general implemented through appropriate multi-feedback topologies. The spreading in the values of time-constants and scaling factors, needed to implement these topologies, increases as the order of the differentiator/integrator and/or the order of the approximation increases. This leads to non-practical values of capacitances and resistances/transconductances in the implementation. A solution to overcome this obstacle is introduced in this paper, based on the employment of a combination of fractional-order and integer-order integrators and differentiators for implementing the desired function. The performance of the proposed scheme is verified through post-layout simulations using Cadence and the Design Kit provided by the Austria Mikro Systeme 0.35μm CMOS technology process. [ABSTRACT FROM AUTHOR]

A quasi-floating gate (QFG) 'super-follower' is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10MHz and power consumption of 120W with a 1.5V single supply. [ABSTRACT FROM AUTHOR]

This paper is devoted to local parametric fault diagnosis of nonlinear analog integrated circuits designed in a bipolar and CMOS technology. An algorithm is proposed that allows estimating values of the considered set of the parameters. The algorithm exploits a diagnostic test performed in a dc state, leading to output voltages measured in the circuit. Each of the output voltages is a parameterized function. A system of overdetermined equations fitting the parameterized functions to the data points is created. An efficient iterative method is developed for solving this overdetermined system of nonlinear equations exploiting the idea of the normal equation and a homotopy concept. It is implemented in the manner that allows operating with the functions not given in the explicit analytical form, which commonly occurs in real nonlinear circuits. For illustration, two examples are given, including a circuit with bipolar transistors and a CMOS circuit designed in a nanometer technology. They reveal the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

An ultra-low voltage sixth-order low pass filter topology, suitable for sensing the T-wave signal in an electrocardiogram (ECG), is presented in this paper. This is realized using a cascade connection of second-order building blocks constructed from a sinh-domain two-integrator loop. The performance of the filter has been evaluated using the Cadence Analog Design Environment and the design kit provided by the Austria Mikro Systeme (AMS) 0.35-µm CMOS process. The power consumption of filters was 7.21 nW, while a total harmonic distortion (THD) level of 4% was observed for an input signal of 220 pA. The RMS value of the input referred noise was 0.43 pA, and the simulated value of the dynamic range (DR) was 51.1 dB. A comparison with already published counterparts shows that the proposed topology offers the benefits of 0.5-V supply voltage operation and significantly improved power efficiency.

Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.

Novel topologies of fractional-order filters, implemented using the internal gate-source capacitance of MOS transistors, are introduced in this paper. This has been achieved using current-mirrors as active elements, resulting into resistorless realizations due to the employment of the small-signal transconductance parameter of the MOS transistor. This also offers the capability for electronic tuning of the frequency characteristics of the derived filter structures. The evaluation of the proposed technique has been performed through the design of a generalized fractional-order filter, which is also digitally programmed in such way that the four standard filter functions are offered. The behavior of the filter has been evaluated using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process. [ABSTRACT FROM AUTHOR]

Design and implementation of CMOS channel select filters for digital video broadcasting-handheld integrated direct-conversion receivers are presented. The filters are designed to fulfill selectivity requirements with optimized power consumption. The proposed filters are based on the current amplifier and the transresistance amplifier offering alternatives for current-mode and voltage-mode signal processing, respectively. Adopting one active element per biquad allows optimization of the power consumption, and hence, leads to significant improvement over the available solutions. The two filters were fabricated in a standard 0.18- \mu \textm CMOS technology and experimental results are provided. [ABSTRACT FROM PUBLISHER]

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 VRMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame. [ABSTRACT FROM AUTHOR]

This paper presents a low power bandgap reference (BGR) with 573 mV average output voltage and 0.95-V minimum supply voltage. Here, the resistor ratio of two types of resistors that have opposite temperature coefficient (TC) realizes a second-order curvature compensation. In addition, to reduce the supply voltage we adopt a voltage divider, and we also employ proportional to absolute temperature (PTAT) voltage generators to reduce the resistor values for low power applications. The proposed BGR fabricated in 65-nm CMOS achieves an average TC of 57 ppm/°C from 0 to 100 °C with 8 samples. The power dissipation at room temperature is 78 nA and the power supply ripple rejection (PSRR) is −67 dB at DC with 1.2 V supply. [ABSTRACT FROM AUTHOR]

Novel topologies of fractional-order generalized filters are introduced in this paper. These offer the following benefits: (1) realization of lowpass, highpass, bandpass, allpass, or bandstop filter functions by the same topology; (2) resistorless realizations; (3) electronic adjustment of their frequency characteristics as well as their order; and (4) employment of only grounded capacitors. All the above have been achieved using Operational Transconductance Amplifiers as active elements and appropriate multi-feedback topologies. The behavior of the proposed designs is verified through simulation results using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35-µm complementary metal-oxide-semiconductor process. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]