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The increasing paradigm shift towards i ntermittent computing has made it possible to intermittently execute d eep neural network (DNN) inference on edge devices powered by ambient energy. Recently, n eural architecture search (NAS) techniques have achieved great success in automatically finding DNNs with high accuracy and low inference latency on the deployed hardware. We make a key observation, where NAS attempts to improve inference latency by primarily maximizing data reuse, but the derived solutions when deployed on intermittently-powered systems may be inefficient, such that the inference may not satisfy an end-to-end latency requirement and, more seriously, they may be unsafe given an insufficient energy budget. This work proposes iNAS, which introduces intermittent execution behavior into NAS to find accurate network architectures with corresponding execution designs, which can safely and efficiently execute under intermittent power. An intermittent-aware execution design explorer is presented, which finds the right balance between data reuse and the costs related to intermittent inference, and incorporates a preservation design search space into NAS, while ensuring the power-cycle energy budget is not exceeded. To assess an intermittent execution design, an intermittent-aware abstract performance model is presented, which formulates the key costs related to progress preservation and recovery during intermittent inference. We implement iNAS on top of an existing NAS framework and evaluate their respective solutions found for various datasets, energy budgets and latency requirements, on a Texas Instruments device. Compared to those NAS solutions that can safely complete the inference, the iNAS solutions reduce the intermittent inference latency by 60% on average while achieving comparable accuracy, with an average 7% increase in search overhead.

Current peripheral execution approaches for intermittently powered systems require full access to the internal hardware state for checkpointing or rely on application-level energy estimation for task partitioning to make correct forward progress. Both requirements present significant practical challenges for energy-harvesting, intelligent edge Internet-of-Things devices, which perform hardware-accelerated deep neural network (DNN) inference. Sophisticated compute peripherals may have an inaccessible internal state, and the complexity of DNN models makes it difficult for programmers to partition the application into suitably sized tasks that fit within an estimated energy budget. This article presents the concept of inference footprinting for intermittent DNN inference, where accelerator progress is accumulatively preserved across power cycles. Our middleware stack, HAWAII, tracks and restores inference footprints efficiently and transparently to make inference forward progress, without requiring access to the accelerator internal state and application-level energy estimation. Evaluations were carried out on a Texas Instruments device, under varied energy budgets and network workloads. Compared to a variety of task-based intermittent approaches, HAWAII improves the inference throughput by 5.7%–95.7%, particularly achieving higher performance on heavily accelerated DNNs.

In the future, mobile systems will increasingly feature more advanced organic light-emitting diode (OLED) displays. The power consumption of these displays is highly dependent on the image content. However, existing OLED power-saving techniques either change the visual experience of users or degrade the visual quality of images in exchange for a reduction in the power consumption. Some techniques attempt to enhance the image quality by employing a compound objective function. In this article, we present a win-win scheme that always enhances the image quality while simultaneously reducing the power consumption. We define metrics to assess the benefits and cost for potential image enhancement and power reduction. We then introduce algorithms that ensure the transformation of images into their quality-enhanced power-saving versions. Next, the win-win scheme is extended to process videos at a justifiable computational cost. All the proposed algorithms are shown to possess the win-win property without assuming accurate OLED power models. Finally, the proposed scheme is realized through a practical camera application and a video camcorder on mobile devices. The results of experiments conducted on a commercial tablet with a popular image database and on a smartphone with real-world videos are very encouraging and provide valuable insights for future research and practices.

Organic Light-Emitting Diode (OLED) technology is regarded as a promising alternative to mobile displays. In this article, we introduce the design, algorithm, and implementation of a novel framework called CURA for quality-retaining power saving on mobile OLED displays. First, we link human visual attention to OLED power saving and model the OLED image scaling optimization problem. The objective is to minimize the power required to display an image without adversely impacting the user’s visual experience. Then, we present the algorithm used to solve the modeled problem, and prove its optimality even without an accurate power model. Finally, based on the framework, we implement two practical applications on a commercial OLED mobile tablet. The results of experiments conducted on the tablet with real images demonstrate that CURA can reduce significant OLED power consumption while retaining the visual quality of images.

In recent years, advances in virtualization technology have enabled multiple virtual machines to run on a physical machine, such that each virtual machine can perform independently with its own operating system. The IT industry has adopted virtualization technology because of its ability to improve hardware resource utilization, achieve low-power consumption, support concurrent applications, simplify device management, and reduce maintenance costs. However, because of the hardware limitation of storage devices, the I/O capacity could cause performance bottlenecks. To address the problem, we propose a hybrid storage access framework that exploits solid-state drives (SSDs) to improve the I/O performance in a virtualization environment.

This paper designs and develops an autopilot system for guiding the trajectory of a small boat as it performs an approaching maneuver within a harbor. In the proposed approach, two canvas targets are arranged in cascade on the berth to serve as leading marks to define the leading line along which to guide the boat toward the berthing standby region. The leading marks are captured by a charge-coupled device (CCD) camera mounted on the bow of the boat, and the resulting image is processed using a color recognition scheme to identify the hue (H) and saturation (S) components. The H- and S-component images are subsequently processed using a noise filtering scheme to accurately detect the location of the two targets in the image. The centers of gravity (CGs) of the two leading marks are then calculated, and the separation distance between them is used to compute the deviated heading angle. This angle is then supplied to an internal model control (IMC) autopilot system as an error signal and is used to generate appropriate control commands to steer the boat toward the leading line. The feasibility of the autopilot system is verified by performing a series of experimental approaching maneuvers using a small boat in a real-world harbor setting.

Mobile systems will increasingly feature emerging OLED displays, whose power consumption is highly dependent on the image content. Existing OLED power-saving techniques change users' visual experience or degrade images' visual quality in exchange for power reduction, or seek a chance to also enhance image quality by employing a compound objective function. This paper presents a win-win scheme that always enhances image quality and reduces power consumption simultaneously. We define metrics to assess the profit and the cost for potential image enhancement and power reduction. Then, we propose algorithms that ensure the transformation of images into their quality-enhanced power-saving versions. Finally, the proposed scheme is realized as a practical camera application on mobile devices. The results of experiments conducted on a commercial tablet with a popular image database are very encouraging and provide valuable insights for future research and practices.

In recent years, virtualization technology enables multiple virtual machines to run on a physical machine, where each virtual machine can run independently and own its operating system. Virtualization technology has been adopted in many IT industries because of its ability to improve hardware resource utilization, achieve low-power consumption, simplify server management, and reduce maintenance cost. However, since the hardware limitation of storage devices, I/O capacity could cause performance bottleneck. In the paper, we will propose a hybrid storage access framework for virtualization environment to dynamically adjust and enhance I/O performance by using solid-state drives (SSDs).

Class-E power amplifiers are widely used especially for constant envelope modulation applications due to their high efficiency even for switching signals with slow rise/fall edges. However, they have been rarely used in CMOS process for very high power levels, resulting from their intrinsic poorer power output capability. In this paper, we propose a unique way to control the drain voltage stress of the active switch device when the rise/fall edges of the driving signal occupy a significant portion of the switching cycle. Our approach employs internal signals within a differential amplifier by inserting a transformer between the two active device branches. Depending on specific process and power supply levels, the stress can be relieved up to more than 20%, which gives significant room for either higher power level and efficiency or using faster (and therefore easier to breakdown) devices.

In this paper, one of the future nonvolatile memory candidates, SONOS with p+-poly gate, has been fully characterized in cell program/erase operation and data retention performance. Novel source-side injection programming and F-N erase schemes have been utilized on both n+- and p+-poly gate, and its characteristics are very satisfactory and can be easily used as a state-of-the-art flash memory. For data retention, our experimental result shows p+-poly does have a slower charge decay rate than does n+-poly gate. This is because of the work function difference between n+- and p+-poly gate that causes the different amount of trapped electrons between two of them. We also predict the charge loss characteristics with various baking temperature for n+- and p+-poly gate, which can tell us the concrete threshold voltage at any read delay time instead of the traditional and inaccurate long time projection from short time status.

In this paper, we will propose a new NAND type SONOS cell structure with high efficiency Source Side Injection programming and F-N erase. This cell is characterized in high scaling abilities, fast program/erase speeds and very satisfactory data retention performances. In consideration of the threshold voltage saturation of the SONOS cell during erase, we use the modified erase bias configuration, DSPE (decrement step pulse erase), to speed up the erase operation and enlarge the memory window without adding any process complexities. To further improve the erase speed, p+-poly gate has firstly been utilized on our NAND type SONOS cell. From our experimental results, p+-poly gate not only prolongs erase threshold voltage saturation to the longer time but improves charge loss characteristics. Instead of traditional threshold voltage extrapolations from short to long time, we applied the time constant model to predict concrete threshold voltage values with various baking time and temperatures.