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125 results on '"CHANG, NORMAN"'

1. A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform

Author

Heidarpur, Moslem, Mirhassani, Mitra, and Chang, Norman

Subjects
Computer Science - Hardware Architecture
Abstract

This paper presents digital hardware for computing polynomial multiplication using Number Theoretic Transform (NTT), specifically designed for implementation on Field Programmable Gate Arrays (FPGAs). Multiplying two large polynomials applies to many modern encryption schemes, including those based on Ring Learning with Error (RLWE). The proposed design uses First In, First Out (FIFO) buffers to make the design fully pipelined and capable of computing two n degree polynomials in n/2 clock cycles. This hardware proposes a two-fold reduction in the processing time of polynomial multiplication compared to state-of-the-art enabling twice as much encryption in the same amount of time. Despite that, the proposed hardware utilizes fewer resources than the fastest-reported work., Comment: art of our code is publicly available at https://github.com/mheidarpur/fpntt

Published
2025

2. Improving Location-based Thermal Emission Side-Channel Analysis Using Iterative Transfer Learning

Author

Lou, Tun-Chieh, Wang, Chung-Che, Jang, Jyh-Shing Roger, Li, Henian, Lin, Lang, and Chang, Norman

Subjects
Computer Science - Machine Learning, Computer Science - Cryptography and Security
Abstract

This paper proposes the use of iterative transfer learning applied to deep learning models for side-channel attacks. Currently, most of the side-channel attack methods train a model for each individual byte, without considering the correlation between bytes. However, since the models' parameters for attacking different bytes may be similar, we can leverage transfer learning, meaning that we first train the model for one of the key bytes, then use the trained model as a pretrained model for the remaining bytes. This technique can be applied iteratively, a process known as iterative transfer learning. Experimental results show that when using thermal or power consumption map images as input, and multilayer perceptron or convolutional neural network as the model, our method improves average performance, especially when the amount of data is insufficient.

Published
2024

3. Novel Preprocessing Technique for Data Embedding in Engineering Code Generation Using Large Language Model

Author

Lin, Yu-Chen, Kumar, Akhilesh, Chang, Norman, Zhang, Wenliang, Zakir, Muhammad, Apte, Rucha, He, Haiyang, Wang, Chao, and Jang, Jyh-Shing Roger

Subjects
Computer Science - Computation and Language, Computer Science - Software Engineering
Abstract

We present four main contributions to enhance the performance of Large Language Models (LLMs) in generating domain-specific code: (i) utilizing LLM-based data splitting and data renovation techniques to improve the semantic representation of embeddings' space; (ii) introducing the Chain of Density for Renovation Credibility (CoDRC), driven by LLMs, and the Adaptive Text Renovation (ATR) algorithm for assessing data renovation reliability; (iii) developing the Implicit Knowledge Expansion and Contemplation (IKEC) Prompt technique; and (iv) effectively refactoring existing scripts to generate new and high-quality scripts with LLMs. By using engineering simulation software RedHawk-SC as a case study, we demonstrate the effectiveness of our data pre-processing method for expanding and categorizing scripts. When combined with IKEC, these techniques enhance the Retrieval-Augmented Generation (RAG) method in retrieving more relevant information, ultimately achieving a 73.33% "Percentage of Correct Lines" for code generation problems in MapReduce applications.

Published
2023

4. A Thermal Machine Learning Solver For Chip Simulation

Author

Ranade, Rishikesh, He, Haiyang, Pathak, Jay, Chang, Norman, Kumar, Akhilesh, and Wen, Jimin

Subjects
Computer Science - Machine Learning, Physics - Fluid Dynamics
Abstract

Thermal analysis provides deeper insights into electronic chips behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming using FEM or CFD. Therefore, there is an urgent need for speeding up the on-chip thermal solution to address various system scenarios. In this paper, we propose a thermal machine-learning (ML) solver to speed-up thermal simulations of chips. The thermal ML-Solver is an extension of the recent novel approach, CoAEMLSim (Composable Autoencoder Machine Learning Simulator) with modifications to the solution algorithm to handle constant and distributed HTC. The proposed method is validated against commercial solvers, such as Ansys MAPDL, as well as a latest ML baseline, UNet, under different scenarios to demonstrate its enhanced accuracy, scalability, and generalizability.

Published
2022

5. A composable autoencoder-based iterative algorithm for accelerating numerical simulations

Author

Ranade, Rishikesh, Hill, Chris, He, Haiyang, Maleki, Amir, Chang, Norman, and Pathak, Jay

Subjects
Computer Science - Machine Learning, Physics - Fluid Dynamics
Abstract

Numerical simulations for engineering applications solve partial differential equations (PDE) to model various physical processes. Traditional PDE solvers are very accurate but computationally costly. On the other hand, Machine Learning (ML) methods offer a significant computational speedup but face challenges with accuracy and generalization to different PDE conditions, such as geometry, boundary conditions, initial conditions and PDE source terms. In this work, we propose a novel ML-based approach, CoAE-MLSim (Composable AutoEncoder Machine Learning Simulation), which is an unsupervised, lower-dimensional, local method, that is motivated from key ideas used in commercial PDE solvers. This allows our approach to learn better with relatively fewer samples of PDE solutions. The proposed ML-approach is compared against commercial solvers for better benchmarks as well as latest ML-approaches for solving PDEs. It is tested for a variety of complex engineering cases to demonstrate its computational speed, accuracy, scalability, and generalization across different PDE conditions. The results show that our approach captures physics accurately across all metrics of comparison (including measures such as results on section cuts and lines).

Published
2021

6. Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation

Author

Li, Henian, primary, Lin, Lang, additional, Chang, Norman, additional, Chowdhury, Sreeja, additional, Mcguire, Dylan, additional, Novakovic, Bozidar, additional, Monta, Kazuki, additional, Nagata, Makoto, additional, Li, Ying–Shiun, additional, S, Pramod M, additional, Yeh, Piin–Chen, additional, Jang, J.–S. Roger, additional, Xi, Chengjie, additional, Jin, Qiutong, additional, Asadi, Navid, additional, and Tehranipoor, Mark, additional

Published
2024
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24. Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis.

Author

KAZUKI MONTA, LANG LIN, JIMIN WEN, SHRIVASTAV, HARSH, CHOW, CALVIN, HUA CHEN, GEADA, JOAO, CHOWDHURY, SREEJA, PUNDIR, NITIN, CHANG, NORMAN, and MAKOTO NAGATA

Subjects
ELECTRIC power, LEAKAGE, POWER resources, INTEGRATED circuits, SYSTEMS on a chip, MAGNETIC fields
Abstract

Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement traces to disclosure, leveraged by a secure system-on-chip design flow toward SC attack resiliency and SC leakage sign off. Power SCLA features the tracking of security sensitive registers within cryptographic logic paths and the automatic assignments of probe points on associated physical power nets. Power supply current traces are efficiently simulated for the large set of input payloads, with direct vector-based and vector-less random switching controls. EM SCLA evaluates magnetic fields created by every piece of metal wiring in metal stacks where power supply current of cryptographic processing flows. The EM emission and EM SCLA from the backside Si surface of an IC chip in flip-chip packaging are experimentally examined with a 0.13 µm test chip. The proposed simulation-based SCLA exhibits the SC leakage metrics of on-chip location and direction dependency as accurately as in the measurements. [ABSTRACT FROM AUTHOR]

Published
2023
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25. Confronting the hard problems in integrated photonic design and simulation

Author

Pond, James, primary, Reid, Adam, additional, McGuire, Dylan, additional, Niegemann, Jens, additional, Novakovic, Bozidar, additional, Wang, Xu, additional, Schelew, Ellen, additional, Duque Gomez, Federico, additional, Alam, Ahsan, additional, Lu, Zeqin, additional, Mahpeykar, Milad, additional, Samadian, Parya, additional, Robertson, Taylor, additional, Dias, Leanne, additional, and Chang, Norman, additional

Published
2021
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28. DNN-based Fast Static On-chip Thermal Solver

Author

Wen, Jimin, primary, Pan, Stephen, additional, Chang, Norman, additional, Chuang, Wen-Tze, additional, Xia, Wenbo, additional, Zhu, Deqi, additional, Kumar, Akhilesh, additional, Yang, En-Cih, additional, Srinivasan, Karthik, additional, and Li, Ying-Shun, additional

Published
2020
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31. Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation

Author

Chang, Keh-Jeng, Chang, Norman H., Oh, Soo-Young, and Lee, Keunmyung

Subjects
Electronic design automation -- Research, Computer simulation -- Models, Strip transmission lines -- Models, Business, Computers and office automation industries, Electronics, Electronics and electrical industries, Spice (Computer simulation) -- Models
Abstract

This paper describes a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced.

Published
1992

33. Applying Machine Learning to Design for Reliability Coverage

Author

Chang, Norman, primary, Chuang, Wentze, additional, Tsavatanalli, Ganesh Kumar, additional, Geada, Joao, additional, Zhuang, Hao, additional, Ramachandran, Sankar, additional, Raian, Rahul, additional, Li, Ying-Shiun, additional, Jia, Yaowei, additional, Kaipanatu, Mathew, additional, Mantena, Suresh Kumar, additional, Shih, Ming-Chih, additional, Yang, Anita, additional, and Jang, Roger, additional

Published
2019
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35. Interaction of RF DPI with ESD Protection Devices in EMS Testing of IC Chips

Author

Tsukioka, Akihiro, primary, Nagata, Makoto, additional, Fujimoto, Daisuke, additional, Miura, Noriyuki, additional, Akimoto, Rieko, additional, Egami, Takao, additional, Niinomi, Kenji, additional, Yuhara, Takesh, additional, Hayashi, Sachio, additional, Srinivasan, Karthik, additional, Li, Ying-Shiun, additional, and Chang, Norman, additional

Published
2018
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42. Simulation techniques for EMC compliant design of automotive IC chips and modules

Author

Tsukioka, Akihiro, primary, Nagata, Makoto, additional, Taniguchi, Kohki, additional, Fujimoto, Daisuke, additional, Akimoto, Rieko, additional, Egami, Takao, additional, Niinomi, Kenji, additional, Yuhara, Takeshi, additional, Hayashi, Sachio, additional, Mathews, Rob, additional, Srinivasan, Karthik, additional, Li, Ying-Shiun, additional, and Chang, Norman, additional

Published
2017
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