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This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution. >

Wave pipelining (also known as maximal rate pipelining) is a timing methodology used in digital systems to increase the number of effective pipelined stages without increasing the number of physical registers in the system. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic. Achieving a high degree of wave pipelining in CMOS technology requires careful study of delay balancing technique involving circuit design, layout method, and testing structure. A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-/spl mu/m technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation. >

Wave-pipelining is a timing methodology used in digital systems to achieve maximal rate operation. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic and maximizing the utilization of the logic without inserting registers. This paper presents a timing constraint formulation for the correct clocking of wave-pipelined systems. Both single- and multiple-stage systems including feedback are considered. Based on the formulation of this paper, several important new results are presented relating to performance limits of wave-pipelined circuits. These results include the specification of distinct and disjoint regions of valid operation dependent on the clock period, intentional clock skew, and the global clock latency. Also, implications and motivations for the use of accurate delay models and exact timing analysis in the determination of combinational logic delays are given, and an analogous relationship between the multi-stage system and the single-stage system in terms of performance limits is shown. The minimum clock period is obtained by clock skew optimization formulated as a linear program. In addition, important special cases are examined and their relative performance limits are analyzed. >

The authors present a high-performance 8 /spl times/ 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption. The multiplier is implemented with MOSIS 2-/spl mu/m technology, and simulation results show a tenfold speed-up over nonpipelined operation.

A high-performance partitionable parallel/pipeline architecture (P/sup 3/A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P/sup 3/A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining. >

Many techniques have been proposed to optimize digital system timing. Each technique can be advantageous in particular applications, however they are most often applied individually rather than concurrently. The framework presented here allows for concurrent timing optimization using retiming, intentional clock skew, and wave pipelining for latch-based designed systems with single or multi-phase clocking. This optimization is formulated as a mixed integer linear program. Our integrated framework also includes a new optimization technique called resynchronization which allows for the insertion of latches in the shortest paths and thus avoids race conditions. Our work has been applied to several designs and is able to significantly reduce the clock period.

This paper describes a DSP based 10BaseT/100BaseTX Ethernet physical layer interface in a 1.8, V 0.18 /spl mu/m single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150 m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6 mm/sup 2/ and consumes 350 mW of power.