Search

International audience; A B S T R A C THeterojunction Bipolar Transistors needed for high-frequency applications require precise dopant control. Insitu doped epitaxies used during device fabrication rely on surface preparation to obtain an optimized dopingprofile. Defects due to imperfect cleaning relates to high emitter resistance and low-frequency noise.Base epitaxy is followed by the fabrication of thin L-shaped oxide spacers and in-situ arsenic-doped emitterepitaxy by Low Pressure Chemical Vapor Deposition. A cleaning step between spacers formation and emitterepitaxy is mandatory to remove residual contamination. Hydrofluoric acid (HF) wet cleaning, in-situ remoteplasma cleaning (SiconiTM) and thermal treatments have been tested. A minimum etching budget is sought forlimiting spacer consumption while adequately cleaning the interface.Time Of Flight-Secondary Ion Mass Spectroscopy (TOF-SIMS) and High-Resolution Transmission ElectronMicroscopy (HR-TEM) are used to characterize the interface and measure levels of arsenic, oxygen, fluorineand carbon. Emitter resistance and base-emitter breakdown voltage measurements are used to show the impacton electrical figures of merit. Siconi targeting 10 Å of thermal oxide removal followed by a thermal treatment(800 ◦C, 60 s) in the deposition chamber results the best process among the tested ones.

With the rising of Hybrid Bonding (HB) as an interesting solution for fine-pitch 3D integration, the influence of process induced variations on performances is a demanding and crucial task. A 3D stacked test vehicle with hybrid bonding pitch ranging from 6.8 down to $1.44\ \mu \mathrm{m}$ was processed and analyzed. A deep analysis on the influence of process variations is conducted and correlated to electrical measurements thanks to a dedicated simulation methodology. This allows a better understating of the process variation parameters that affects electrical resistance and capacitance along with their relative importance which is essential for optimization. The common parameter affecting both capacitance and electrical resistance is Wafer-to-Wafer overlay between top and bottom wafers arising the need for high accuracy in bonding alignment. The quality of the hybrid bonding interface is discussed thanks to the simulation model, before and after robustness tests depending on hybrid bonding pitch, leading to an estimation of contact resistivity around $2. 10^{-10}\Omega.cm^{2}$ for the $1.44\ \mu \mathrm{m}$ -pitch structure.

In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296 mV@Vdd 1.1 V.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz f T and 370 GHz f MAX associated with a CML ring oscillator gate delay τ D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

Magnetic tunnel junctions with a barrier of magnesium oxide were prepared by plasma oxidation of sputter-deposited magnesium. They show magnetoresistance ratios up to 4.5% at room temperature and 5.5% at low temperatures for barrier thickness of 1.6 nm. The material exhibits low barrier heights of around 0.7 eV. These junctions follows the predictions of the free electron model which contrast with the predictions of band structure calculations and experimental results on epitaxial MgO based tunnel junctions.

In this paper we explore the impact of the parasitic bipolar in undoped channel Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The static parasitic bipolar latch occurs at a drain bias superior to the circuit operation alimentation. The several type of ground plane and forward or reverse back biasing do not modify significantly the bipolar breakdown voltage. The thicker EOT gate oxide is more sensible to parasitic bipolar breakdown. Finally, results have been reinforced by using calibrated TCAD simulation tool.

Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical threshold voltage (V T ∼0.45V) for both NMOS and PMOS devices [1], still one major challenge is to provide V T modulation with an undoped channel in order to satisfy the low power (LP) circuit design requirements [2–5]. To overcome this issue, combining UTBOX substrate with ground plane (GP) has been proposed [2,5]. However this technique with midgap metal gate requires a FBB biasing in order to realize low V T that's implies a disruptive circuits design to avoid forward diode biasing in the substrate between the two opposite GP type beneath the BOX [6]. In order to introduce more V T modulation flexibilities and especially for LVT PMOS and HVT NMOS, aluminum Oxide (Al 2 O 3 ) inserted in TiN gate stack has been proposed for bulk devices [7–8] in a gate first process. The viability of this option is studied in this paper for FDSOI, for HfO 2 and HfSiON gate oxide, through transistors performance, reliability and variability analysis.

We demonstrate for the first time high-performant planar multi-gates devices with Si-conduction channel of 4nm, allowing drive current up to 1350µA/µm @I off =0.4nA/µm (V dd =1.1V, CET=1.9nm). But as future multi-gates transistors need to have reduced capacitances and a simple robust process, we also demonstrate in this paper an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.

For the first time, Multi-V T UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I ON current improvement by 45% for LVT options at an I OFF current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um2 bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm2 SRAM bitcells the effectiveness (ΔV T versus V b ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17A/V dd 1.1V and 29A/V dd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IP's required in a SOC are demonstrated for LP applications.

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

This paper demonstrates, for the first time, that sub-atmospheric chemical vapour deposition (SACVD) oxide is a good candidate for 45-nm node as shallow trench isolation (STI) gap-fill as well as a mobility enhancement technique for both lang100rang and lang110rang channel orientations. Respectively, 11% and 18% drive current enhancement for NMOS and PMOS transistors as well as a 12% ring oscillator speed improvement compared to a conventional high density plasma (HDP) process are reported

Low-resistance magnetic tunnel junctions with an $\mathrm{Mg}\mathrm{O}\text{\ensuremath{-}}{\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ composite tunnel barrier have been grown. From the theoretical point of view, current-voltage and magnetoresistance-voltage characteristics are predicted to be asymmetric. These asymmetries are studied as a function of barrier thicknesses for given experimental MgO and ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ barrier heights. From an experimental point of view, the bottom alumina barrier acts as a diffusion barrier allowing the complete oxidation of the thin deposited Mg layer. As a result, composite ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}∕\mathrm{Mg}\mathrm{O}$ tunnel barriers show a lower area resistance and a magnetoresistance signal at nonzero applied voltage that is predicted to be equivalent as single ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}$ tunnel barriers with the same total thickness. Current-voltage and magnetoresistance-voltage characteristics are shown to be asymmetric at high voltages.