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A2RAM devices are fabricated using an adaptation of Si-Nanowire process flow. They include a Si-SiGe heterostructure to improve memory performance. Even the device structure is not exactly what we expect, we succeed to evidence 1T-DRAM programming.

We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m matching, $A_{v0}=62dB$ gain (L=200nm), $f_{T}=126GHz$ cut-off frequency and $f_{MAX}=182GHz$ maximum operating frequency (L=35nm). Junction Less transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hotcarrier degradation and fMAX. This is explained by junction less physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

In this paper, we experimentally demonstrate, for the first time, gate-all-around (GAA) nanosheet transistors with a record number of stacked channels. Seven levels stacked nanosheet (NS) GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show an excellent gate controllability with extremely high current drivability $(3\mathrm{mA}/\mu \mathrm{m}\ \mathrm{at}\ \mathrm{V}_{\mathrm{DD}}=1\mathrm{V})$ and a 3 x improvement in drain current over usual 2 levels stacked- NS GAA transistors.

This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raised source drain epitaxy) that were considered as potential showstoppers for this technology have shown decisive progress very recently.

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high- $\kappa$ metal gate process and self-aligned-contacts. Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

The fabrication of Si0.7Ge0.3 sub-10 nm nanochannels in gate-all-around devices requires a highly selective Si isotropic etching process. The etching of Si selectively to Si0.7Ge0.3 with CF4/N2/O2 downstream plasma has been investigated using various morphological and surface characterization techniques. Conditions such as 400 W microwave power, 700 mTorr pressure, 25 °C chuck temperature, and 22% CF4:22% N2:56% O2 feed gas mixture were found to be optimum for selectivity and etch rates. X-ray photoelectron spectroscopy showed that, during the etching process, a highly reactive 8 nm thick SiOxFy layer is formed on Si. Meanwhile, a 2 nm thick passivation layer is observed on SiGe. The latter is a mixture of SiOxFy and GeOxFy species that protected the alloy from etching. The process selectivity was improved by investigating different wet and dry oxidant treatments prior to etching. The dry oxidant treatment gives the best results in terms of selectivity. These results obtained on blanket wafers have been validated on pattern wafers. Scanning electron microscopy demonstrated that SiGe nanowires were fully released with a high selectivity after dry oxidation followed by the etching process.

Context. Within the framework of the second-generation instrumentation of the Very Large Telescope Interferometer of the European Southern Observatory we have developed the four-telescope beam combiner in integrated optics. Aims. We optimized the performance of such beam combiners, for the first time in the near-infrared K band, for the GRAVITY instrument dedicated to the study of the close environment of the galactic centre black hole by precision narrow-angle astrometry and interferometric imaging. Methods. We optimized the design of the integrated optics chip and the manufacturing technology as well, to fulfil the very demanding throughput specification. We also designed an integrated optics assembly able to operate at 200 K in the GRAVITY cryostat to reduce thermal emission. Results. We manufactured about 50 beam combiners by silica-on-silicon etching technology. We glued the best combiners to single-mode fluoride fibre arrays that inject the VLTI light into the integrated optics beam combiners. The final integrated optics assemblies have been fully characterized in the laboratory and through on-site calibrations: their global throughput over the K band is higher than 55% and the instrumental contrast reaches more than 95% in polarized light, which is well within the GRAVITY specifications. Conclusions. While integrated optics technology is known to be mature enough to provide efficient and reliable beam combiners for astronomical interferometry in the H band, we managed to successfully extend it to the longest wavelengths of the K band and to manufacture the most complex integrated optics beam combiner in this specific spectral band.

International audience; This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

International audience; We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.

Best paper award; session 9: Novel Materials and Technologies; International audience; Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

International audience; We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.

A three dimensional 300mm wafer scale nano imprinting lithography was developed. Two process flows were investigated to manufacture sub 100nm resolution multilevel silicon stamps. Using 193nm optical lithography and dry etching processes in a standard Integrated Circuit pilot line, we succeeded in manufacturing 5 levels stamps. Depending of the pattern designs and number of required levels onto the stamp, we proposed manufacturing process rules. We also demonstrated that sub 20nm overlay accuracy over 300mm wafer was achievable between each level patterned into the stamp. These 3D stamps were then printed over 300mm wafer coated with 200nm thick thermoplastic resist layer. We demonstrated that large surface 3D printing with sub 100nm resolution was achievable with an equivalent patterning throughput of 4cm^2/s. Both the use of silicon hard and polymer soft 3D stamps were investigated to underline the impact of the stamp's mechanical stiffness onto the residual layer thickness distribution over large surfaces.

M.Casse, S. Barraud, R. Coquand, M. Koyama, D. Cooper, C. Vizioz, C. Comboroure, P. Perreau, V. Maffini-Alvaro, C. Tabone, L. Tosti, S. Barnola, V. Delaye, F. Aussenac, Ghibaudo, H.Iwai, G. Reimbold 1 CEA-Leti, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France 2 STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France 3 IMEP-LAHC, INPG-MINATEC, 3 parvis Louis Neel, 38016 Grenoble, France 4 Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama, Japan email: mikael.casse @cea.fr

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

session 8: advanced CMOS and New Devices Concepts; International audience; Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels.

Due to the unavoidable short channel effects associated with planar bulk silicon MOSFET scaling, FinFET and FDSOI have become the most used solutions for the latest generations of CMOS. Gate control over the channel is excellent and performances are enhanced due to the increased effective width in the case of FinFET [1], and due to the forward body biasing solution in the case of FDSOI. However, after several generations of industrially produced FinFET and FDSOI, one crucial question will arise: how far can those technologies be scaled down? Currently, nanowire (NW) transistors have been proven to be excellent candidates for advanced technology nodes. Specifically, electrostatic control is improved over FinFET for better performance and energy savings. Over the last ten years, many developments on nanowire fabrication and nanowire FETs have been proposed [2] [3] [4] [5]. Today, stacking several nanowires at such scale paves the way for a significant increase in the effective width and current density along with substantial savings in device footprint. Stacked nanowires can be implemented with different geometries such as circular or square cross-sections. However, we recently confirmed [5] among other studies [6] that thin and wide devices, also labelled as nanosheets, provide the best performances with respect to the FinFET technology. A further attractive aspect for the use of nanowires in transistors, is that it may be possible to keep some of the flexibility from the planar technologies. In contrast, FinFET technology imposes a discrete partitioning of the active area. In order to increase the output current of a given FinFET based gate, it may be necessary to add another fin to increase the footprint by one fin pitch. Using nanosheets transistors, channel width can be tuned to obtain the required amount of current with limited impact on footprint as discussed in [7]. Stacked nanowire technology is also appealing as one possible solution due to the fact that their integration can be derived from FinFET. Several groups are currently working on their integration trying to minimize the variations from FinFET Gate-Last process [8]. Two options were identified and labelled as NW first and NW last referring to the fabrication of the NW stack. In the former, several successive epitaxies are performed and patterned to form the active zone as a vertical fin, after which silicon or silicon germanium needs to be removed in order to leave suspended silicon or silicon germanium channels. In the NW last integration, selective removal of silicon germanium happens in between the spacers after the removal of the sacrificial gate. In this case, an etch stop layer must be created to prevent the final gate penetrating under the spacers. This etch stop layer must also be low K in order to recreate the missing spacer material in between the NWs. Due to this requirement, an alternative integration has also been investigated. In the NW first option the selective removal of silicon germanium is done before the first spacer patterning and deposition. This method is also coupled with the use of a hydrogen silsesquioxane (HSQ) resist. This flowable oxide can be exposed through the silicon nanowires and the remaining material left after developing can be used as a sacrificial gate during the gate last process. The spacer deposited afterward is able to wrap around the NWs and the oxide temporary gate. As a consequence, this method provides self-aligned gate and spacer. In recent years, we have also come to focus on carrier transport in NW devices. We have produced several NW-FETs in trigate and Ω-gate shapes on SOI in which we measured electron and hole mobility. Face related transport was observed and improved by using proper strain engineering. Strained SOI and silicon germanium raised source and drain were found to have a significant impact on mobility [4]. Currently, this work is also being integrated in order to boost the performances of our stacked NW-FETs. In this paper we propose a review of the NW architecture and of different integration concepts. Several key points for the performance optimization will be pointed out. [1] Natarajan, S. et al. IEDM, 2014 [2] Ernst, T. et al. IEDM 2006 [3] Coquand, R. et al. VLSI 2013 [4] Barraud, S. et al. VLSI 2013 [5] Gaben, L. et al. SSDM 2015. [6] Kim, Seong-Dong et al. S3S 2015 [7] Lacord, J. et al. SSDM 2012. [8] Lauer, I. et al. VLSI 2015

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.

This paper presents a new top-down method to fabricate Ge-rich nanowires for multi-channel devices by Ge enrichment technology. 3 dimensional Ge nanowire stacks have been fabricated and characterized by SEM, TEM, EDX. Nanowires obtained are single crystalline with no crystalline defects observed on cross-sectional TEM pictures. The main advantage of this method is that the shape, the size and the concentration of Ge nanowires can be tuned by process parameters. Indeed, depending on these parameters, nanowires with a Ge content up to 100% can be obtained with a very aggressive diameter (as low as 10nm). Moreover, this technology allows the co-integration of Ge and Si nanowires for pMOS and nMOS devices, respectively.

An original technique is used to induce a compressive strain in the channel of Fully Depleted (FD)SOI MOSFETs thanks to an Embedded Buried Nitride stressor. Strain measurements are performed by Grazing Incidence X-ray Diffraction (GIXRD) and compared to mechanical simulations. Both results are in agreement and prove that the strain level can achieve -0.6 percent (-780 MPa) in the channel of a transistor, depending on the active region geometry and the nitride properties (intrinsic strain and thickness). This technique is thus very promising in order to boost pMOSFETs on thin films.

This article highlights some aspects associated with the fabrication of stacked nanowire metal oxide semiconductor field effect transistors (MOSFETs) and more precisely the active area conception. These novel architectures, with gate-all-around or independent gates (ΦFET), are promising solutions to improve electrostatic control with high on-current (Ion) and to reduce power consumption for sub-32-nm transistors. Their fabrication is highly complex regarding lithography and etching. For this study, stacked nanowires were achieved by using hybrid lithography (e-beam/deep ultraviolet) combined with anisotropic and isotropic etchings of a Si∕SiGe multilayer to form suspended silicon nanowires. Therefore, we needed high aspect ratio resist features in order to perform the anisotropic etch of the Si∕SiGe multilayer (thickness: 250nm). For this purpose, we compared two ways to pattern the sub-32-nm silicon stacked nanowires. On one hand, a resist trimming was performed on thick large critical dimension patterns...

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.

The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport properties of Si (SiGe) NWs and the critical contribution of strain are discussed. A particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high-density stacked-NWs architectures.

In this paper we report on advances in DUV dry photolithography both for etching and implantation of silicon photonic devices. We explain why silicon patterning is a critical building block in silicon photonics and what are the challenges related to that process. Furthermore, it also occurs that some silicon photonic devices need implantation lithographic conditions which are also specific to the technology. For that purpose, we developed a dedicated DUV 193nm implantation lithography to address that need.

The impact of nanowire (NW) height and Si 0.7 Ge 0.3 :B source-drain (S/D) on the performance of p-type trigate NW is presented. We show that an increase in Si NW height from 14.5nm to 24nm generates up to +30% enhancement in hole effective mobility for a 13nm NW width. Effectiveness of Sio.7Geo.3:B S/D is then discussed for a wide range of NW width (13nm Nw 0.7 Ge 0.3 :B S/D: +86% I on improvement is observed for H Nw =11nm against only +58% for H Nw =24nm.

The selective removal of a SiGe sacrificial layer in a Chemical Dry Etching (CDE) mode is reported. The process parameters have been optimized in order to minimize the consumption of the surrounding Si in advanced 3D structures. The impact of parameters such as the Ge content, the SiGe layer's thickness or the nature of the mask has also been investigated in order to have a global understanding of the etching mechanisms. The optimal process conditions have been tested on devices of which electrical performances have completed the morphological characterization of the etching recipe.

High carbon content Si1-yCy layers, with substitutional C concentration as high as 2% and almost no interstitial C atoms (

In this letter, the electrostatic and the performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated. The impact of silicon nitride (SiN) spacer thickness (7, 10, or 15 nm) on short-channel performance is examined. The tradeoff between superior electrostatic confinement and electrical performance, which will be an essential consideration for the design of future NW devices, is clearly observed. Finally, a comparison with trigate NWs shows an improved electrostatic control for a cylindrical-shaped gate, as theoretically expected.

Ω-gate nanowires (NW) P-FETs on compressively-strained-SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (L G =15nm and W NW =25nm) with an outstanding I ON current (I ON =860µA/µm at I OFF =140nA/µm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si 0.8 Ge 0.2 -channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for L G =30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at L G =15nm.

session 8: Beyond CMOS; International audience; We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si 1-x Ge x (x=0, 0.2, 0.25) nanowires, Si 0.7 Ge 0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W -3 dependence of ON current (I ON ) per wire. The fabricated devices exhibit higher I ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.

We demonstrate the feasibility of producing advanced silicon photonic devices for future data communication nodes at 40Gbps using CMOS compatible processes in a 300mm wafer fab. Basic building blocks are shown together with various wavelength division multiplexing solutions. All the devices presented are integrated on 220nm SOI or locally grown epitaxial germanium.

Thanks to a well-controlled CMOS FDSOI technology we have recently been able to demonstrate breakthroughs in the combined use of field effect and Coulomb blockade phenomena. On one hand, we have demonstrated room temperaturehybrid circuits based on single electron transistors and MOSFETs. On the other hand, we have shown the practical performance of electron pumps designed with a single silicided Coulomb island and MOSFETs as tunable barriers for metrologic applications.

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness ( H ) and nanowire width ( W ) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (1 0 0) top surface and (1 1 0) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (subthreshold slope and drain-induced-barrier-lowering) of scaled down TGNW FET is clearly demonstrated.

In this paper we show that on scaling nanowire width from 20 nm down to sub-7 nm regime, together with achieving excellent short channel effect control (DIBL = 12 mV/V for LG = 20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing ID–VG of a FET to oscillating ID–VG of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD = ±0.9 V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices.

We report an experimental study of the carrier transport in [1 1 0]-oriented long channel tri-gate (TG) and omega-gate (ΩG) silicon nanowire (SiNW) transistors cross-section down to 11 nm × 10 nm. Electron and hole mobilities have been measured down to 20 K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10 nm width.

We demonstrate the first Single Electron Transistor (SET) with high-k/metal gate operating at room temperature (at V D =0.9 V) cointegrated with fully depleted SOI (FDSOI) MOSFET (with 20 nm gate length) to realize a hybrid SET-FET circuit. Our resulting circuit exhibits typical SET oscillations upto record milliampere range. We also demonstrate a SET-FET based Negative Differential Resistance (NDR) device with 104 peak-valley-current-ratio and also a literal gate for multivalued logic applications.

The operation of hybrid circuits consisting of a single hole transistor coupled to a metal oxide semiconductor field effect transistor (MOSFET) is demonstrated at 350 K. The devices are designed at ultimate scaling with complementary metal oxide semiconductor technology on 300 mm diameter silicon on insulator wafers using deep ultra-violet lithography. Coulomb blockade oscillations up to 350 K are measured from silicon nanowire transistors with 20 nm Ω-gate length and diameter under 5 nm. These oscillations are exploited to produce inverter/amplifier, literal gate, negative differential resistance and memory loop circuits for multivalued (MV) logic and MV memory applications, via hybridization with MOSFET in SETMOS configuration. The fabrication and the operation of these SHT-MOSFET hybrid circuits at high temperature should spur single charge transistor integration into circuits for innovative applications in nanoelectronics.

For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for L G =20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked I D -V G 's. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at V D =±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.

A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H 2 annealing used for Ω-Gate. On short gate length, a strain-induced I on gain as high as 40% at L G =45nm is achieved for multiple-NWs active pattern.

In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

This paper reports on ultra-scaled single-crystal Si NEMS resonators (25–40nm thick) operating in the 10–100MHz frequency range. Their first monolithic integration at the front-end level with CMOS enables to extract the signal from background leading to possible implementation of direct/homodyne measurement, for high sensitivity sensing applications and portable systems.