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The structure of the distributed computing ATPG system DPLATON is presented, with special emphasis on the distribution strategy basis and the communication structures implemented. The proposed system is based on a dynamic fault list partition criterion. The standard remote procedure call (RPC) and external data representation (XDR) mechanisms have been adapted to construct an efficient dynamic distributed implementation. Reduced test sets and important CPU time speedup factors are reported. >

This paper presents a new approach to a distributed ATPG system for large combinational circuits. Although several ATPG parallel implementations have been developed, many of them rely on the use of very specialized and expensive hardware. However, the proposed implementation is built over an heterogeneous network of workstations, which is normally available at all design labs. The proposed parallelization scheme is based on an integrated random and deterministic test vector generation/fault simulation environment, combined with an efficient fault list partitioning strategy and a dynamic communication structure. Reduced numbers of test vectors and significant speed-up factors are reported. >

Describes the architecture of a binary multiplier that, because of its intrinsic regularity and simplicity, may be extended for any number of bits. It is a modification of the array of full adders scheme, which allows the operation with two's complement numbers in systolic mode. The design has been validated and implemented in the SOLO 1400 environment, using ES2 standard cells. Laboratory prototypes perform a multiplication every 24 ns. Finally, a preliminary evaluation of a full custom version is presented.