Search

International audience; A new protocol based on Y-function is used for accurate statistical extraction of electrical parameters of High Electron Mobility Transistor (HEMT) devices for GaN technology. This protocol presented here is used for extraction of relevant electrical parameters such as oxide capacitance, threshold voltage, effective mobilities and access resistance. This study has been verified over a large range of channel lengths for two normally-off HEMT GaN wafers having different levels of access resistances.

The fully recessed gate GaN-on-Si MOS-channel HEMTs (MOSc-HEMT) with Back-Barrier (BB) structure gives rise to unexpected threshold voltage (V TH ) behaviors such as V TH increase with decreasing gate length (L G ) (V TH roll-up) and discrepancies between V TH values extracted from I D (V G ) (V TH_IV ) and from C GC (V G ) (V TH_CV ) characteristics. Using TCAD simulations and experimental measurements, we demonstrate that conduction band confinement, especially at gate corners, is responsible for these peculiar V TH behaviors. This band confinement is strengthened by the fully recessed gate configuration coupled with the proximity of a back-barrier.

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al 2 O 3 /UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split- CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm−3) thin layer at the bottom for extremely small body thickness (TSi

In this paper, we study the ambipolar tunneling signature from the output characteristics of TFETs featuring Si 0.8 Ge 0.2 homojunctions, which we compare to those measured on conventional MOSFETs and Schottky Barrier FETs. The difference with the former is immediate since a single TFET can display a transistor effect under both pull-up (nTFET) and pull-down (pTFET) biasing conditions. This is however a property shared with SBFETs, in which injection occurs via tunneling through a single carrier Schottky Barrier instead of band-to-band tunneling. Without requiring quantitative considerations on the current levels or transfer characteristics, we find that simply performing the same dual I D – V DS electrical tests while voluntarily “swapping” the S/D terminals unequivocally characterizes TFET operation, even compared to asymmetrically doped SBFETs.

session: 3D technology II; International audience; Tunnel FETs fabricated using the low-temperature Cool Cube TM process are compared with devices made with standard high-temperature (HT) technology. Charge pumping (CP) and low-frequency noise (LFN) measurements were performed to evaluate the impact of low-temperature (LT) process on the device performance. LT devices feature a higher density of source/drain junction defects, due to lower thermal budget, causing higher levels of LFN. These defects enhance the trap-assisted tunneling (TAT) current which is further amplified by the more abrupt junctions obtained using LT processing.

International audience; This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration S. Maitrejean,a,z N. Loubet,b E. Augendre,a P. Morin,b S. Reboh,c N. Bernier,c R. Wacquez,a B. Lherron,b A. Bonnevialle,c,d Q. Liu,b J. M. Hartmann,c,∗ H. He,e A. Halimaoui,d J. Li,e S. Pilorget,b J. Kanyandekwe,b L. Grenouillet,c F. Chafik,b Y. Morand,d C. Le Royer,c O. Faynot,a M. Celik,b B. Doris,e and B. De Salvoa

session 17: CMOS integration; International audience; We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (R ACC ) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on R acc (-21% for 4 V V B and -53% for -1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ε n/p =0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.

session 4: Memory Devices; International audience; We review the operation mechanisms of the Z 2 -FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.

session 1: Nanoscale FETs; International audience; We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage (VTH) of p-mode operating TFETs shows a 300 mV reduction with similar ON state currents (wrt HT reference), opening path towards optimized devices (very low VTH & supply voltage VDD).

We demonstrate, for the first time, the 3D Monolithic (3DM) integration of In 0.53 GaAs nFETs on FDSOI Si CMOS featuring short-channel Replacement Metal Gate (RMG) InGaAs n-FinFETs on the top layer and Gate-First Si CMOS on the bottom layer with TiN/W inter-layer contacts. State-of-the-art device integration is achieved with the top layer InGaAs utilizing raised source drain (RSD) and the bottom layer CMOS having Si RSD for nFETs, SiGe RSD for pFETs, implants, silicide and TiN/W plug contacts. The top layer InGaAs n-FinFETs are scaled down to L g =25 nm and both the Si nFETs and pFETs in the bottom layer are scaled down to L g ∼15 nm. Finally, utilizing the inter-layer contacts, we demonstrate a densely integrated 3D 6T-SRAM circuit with InGaAs nFETs stacked on top of Si pFETs showing considerable area reduction with respect to a 2D layout.

The ‘BOX creep’ technique consists in introducing stress in a SOI layer by taking advantage of the creep of the buried oxide enabled its low viscosity at high temperature. In this study, we deeply investigate the impact of the structure geometry and parameters on the efficiency of creep through mechanical simulations. We find that a 1.1GPa stress can be achieved for an active length of 400nm. This result shows that BOX creep can be an efficient way to boost the performance of future FDSOI technology generations.

300 mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5 nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as the channel of advanced Fully Depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET). We present in the first part the successful fabrication of 5 nm SGOI wafers. Various characterization techniques are used to investigate the Ge profile and the final strain in the fabricated 5 nm Si 0.7 Ge 0.3 film. Secondary Ions Mass Spectrometry (SIMS) and Scanning Transmission Electron Microscopy (STEM) clearly show that the Ge content is very homogeneous ( x Ge = 30 ± 1%) in the SiGe layer. Raman spectroscopy and High Angle Annular Dark Field (HAADF) STEM both confirm that the 5 nm thick SiGe film is compressively strained (−2 GPa). The second part is dedicated to the sensitivity of the Ge enrichment process (based on numerical modelling). We investigate the impact of single and combined fluctuations of the pre-structure parameters ( T Si , T SiGe,0 , x Ge,0 ) on the final SiGe layer ( T SiGe , x Ge ).

We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment. Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography. When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances. At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage VDD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption.

SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) [1] and ultra-low power Fully Depleted (FDSOI) [2], the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology [3]. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.

We report the fabrication and the characterization of tunnel FETs fabricated on SiGe-On-Insulator with a High-κ Metal Gate (HKMG) CMOS process. The beneficial impact of low band gap SiGe channel on I D ( V G ) characteristics is presented and analyzed: compressive Si 0.75 Ge 0.25 enables to increase by a factor of 25 the saturation currents, even at small gate length ( L G = 50 nm). This large gain is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels).

cited By 1; International audience; Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile channels. We present an alternative technique to blanket sSOI substrates. The efficiency of the “Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI” technique has been previously successfully demonstrated on blanket SOI (+ 1.6 GPa tensile strain achieved). Here we demonstrate a simple and efficient STRASS module integration in an advanced FDSOI route (14 nm design rules) which allows to cointegrate tensile Si for nFETs and unchanged pFETs. After pFETs have been protected (SiN), the STRASS technique has been used in the SOI nFET patterns. This process requires SiGe selective epitaxy, buried amorphization by ion implantation, recrystallization and SiGe removal. Raman spectroscopy is used to characterize the stress in Si areas with respect to process conditions (implantation, active area dimensions). Moreover, the mechanisms of SiGe relaxation will be discussed as function of device dimensions and SiGe layer properties (thickness, Ge content). We demonstrate the successful integration of localized STRASS module: tensile Si patterns (for nFETs) with a level of stress of + 1.6 GPa, cointegrated with unmodified pFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim). Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

cited By 1; International audience; We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. 'STRASS' and 'BOX creep' techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-The-Art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: The electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles. © 2016 IEEE.

We experimentally studied the high-field transport and mobility in nanoscaled Si1 -xGex/silicon on insulator (SOI) PMOSFETs with gate length down to 17 nm. The study relies on the electrical characterization performed from room temperature down to 20 K. Strain relaxation in short channel has been evidenced by nanobeam electron diffraction, which explains the decrease of hole velocity and mobility with gate length. Despite this strain relaxation, a mobility gain is nevertheless preserved in sub-100-nm SiGe PMOS, with a maximum gain for 20% Ge in the layer. Short-channel mobility extraction reveals a lower contribution of Coulomb scattering for SiGe channel PMOS, which may explain this mobility improvement. We also demonstrate that the short-channel transport is governed by the Ge composition in the SiGe layer, with an optimum concentration of 20% Ge. We have finally evidenced a different temperature dependence of the limiting velocity at high field between SiGe and Si PMOS, suggesting that SiGe transport will be governed by inelastic scattering instead of ballisticity as L is shrunk.

This paper presents a wide experimental study of hole transport in SiGe pMOSFETs. Various Ge contents, from 20% up to 60%, and growth templates [unstrained or tensely strained silicon-on-insulator (SOI)] were screened in order to study the influence of various strain levels and Ge concentrations. Electrical results have been compared with the amount of strain in the channel, characterized through dark-field electron holography and nano-beam electron diffraction. The SiGe channel/oxide interface has been investigated through spectroscopic charge pumping and low temperature measurements. We found the signature of Ge-induced defects, particularly near the valence band. The different scattering mechanisms limiting the hole mobility in long-channel transistors have been decorrelated and discussed in the light of the different experimental data provided. We have shown in particular the low contribution of alloy scattering in the SiGe devices under study, and that carrier transport is dominated by the strain effect for Ge content up to 40%. The roughness parameters of the SiGe channel/oxide interface are also modified, with a less prejudicial impact on mobility. The effect of strain and Ge content on the different scattering mechanisms has been established. The combination of all the scattering contributions leads to a maximum mobility at room temperature for a Ge content xGe = 0.4 on an SOI template, or equivalently, xGe = 0.6 on a strained SOI template.

We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current I D . We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured I D over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/ f 2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.

We report an original Dual Strained Channel On Insulator (DSCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/c-SiGe/(s)SOI with a TiN/HfO 2 gate stack (EOT = 1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off ( I ON + 23% for a given I OFF = 100 nA/μm), and thus to obtain similar I ON for n and pFETs (∼650 μA/μm at V DD = 1 V). Meanwhile, thanks to a channel material/strain engineering, the threshold voltages are adjusted ( V th ∼ ±0.2 V) for high performance (HP) CMOS with a single mid-gap metal gate. Extracted interface trap densities ( N T = 5–8.5 × 10 17 cm −3 eV −1 ) using low frequency noise indicate the excellent integrity of the TiN/HfO 2 stack when compared to SOI reference samples.

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.

In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.

SiGe and Ge based CMOS are very attractive for the sub-22nm nodes. In this paper we discuss the challenges regarding the integration of these materials in the channels of advanced MOSFETs. After a review of the recent achievements in the field of SiGe and Ge based substrates, we focus on the different solutions that enable to obtain SiGe and Ge channel MOSFETs and on the status concerning the best high mobility CMOS (from cSGOI and GeOI MOSFETs to DualChannel CMOS). After this topical outline, we conclude on the possible ways for SiGe and Ge to replace Si for very aggressive nodes.

We present a methodology for accurate calculation of effective electric field in Ge and GeOI (Germanium-on-Insulator) pMOSFETs, based on the experimental determination of the parameter η, linking the inversion charge and the effective field. The fabrication procedure of wafers and devices is described. The novel extraction methodology for η factor has been validated experimentally for both bulk-Ge and fully-depleted (FD) GeOI MOSFETs. A difference in η of 20% has been found between the two structures. This correction has a significant impact on effective mobility analysis for advanced GeOI-based pMOSFETs. Furthermore, the influence of the temperature on η parameter has been investigated. The analysis reveals the behavior of the surface roughness limited mobility, which appears to be independent on T and to vary as a function of E eff - 1 for holes in Ge. An appropriate Coulomb limited mobility modelling is finally proposed, providing relevant information on the interface trap charge in undoped GeOI pMOSFET devices.

Simulations of germanium-on-insulator fully-depleted pMOSFET have been performed from process to device using 2D Silvaco software and compared with experimental results. A comprehensive study of these experimental results allows enlightening the specificity of GeOI devices and leads to a good description of electrical output characteristics at low and high drain-to-source voltage and for various gate lengths. More specifically, the adaptation of mobility model from silicon to germanium, a correct description of interface trap densities and a good consideration of leakage current mechanisms are the main challenges addressed in this paper for GeOI pMOSFET simulation.

The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power, high performance and increased functionalities. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to reduce power consumption and manage low supply voltage. Multigate architectures increase MOSFETs drivability, reduce power, and allow new memory devices opportunities for future applications. By introducing new materials(HiK, Ge, III-V, Carbon based materials like diamond, graphene and CNTs, molecules,…), and new functions such as sensing and actuation allowing to interface the outside world (M/NEMS, filters, Imagers,…), Si based CMOS will be scaled beyond the ITRS as the System-on- Chip/Wafer Platform. The Heterogeneous integration of these devices with CMOS will require new 3D and Packaging schemes leading to the increase of effective packing density, improving systems figures of merit. Index Terms- CMOSFETs, Diamond, Germanium, Nanocrystals, Flash Memories, Silicon on insulator technology, Strain, Wafer bonding, Heterogeneous, MEMS, NEMS, BAW, RF, Switch, Optical interconnect, Imagers, 3D-TSV, 3D SOW. The International Technology Roadmap of Semiconduct three types of products: High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) devices. In the HP case, an historical fact happens by the 32nm node: the contribution of static power dissipation become close to the dynamic power somewhat this evolution by improving the saturation current to leakage current ratio. In this review, we will first analyze the main limitations and showstoppers affecting CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new devices architectures(FDSOI or multigate devices) are discussed. Low power consumption and Heterogeneous functions integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, leverage 3D IN Package or ON chip co-integration.

In this brief, the hole transport properties of narrow-width germanium-on-insulator (GeOI) pMOSFETs are investigated. We report, for the first time, +65% low-field hole mobility enhancement in narrow-width (0.29-mum effective widthW eff) versus large-width (10- mum W eff) GeOI mesa-isolated devices. The observed enhancement, which is independent of the device length down to 90 nm, is attributed to improved sidewall transport properties resulting in higher hole mobility on the sides than on the top of the devices. At high inversion charge density N inv~ 1013 cm-2, + 55% hole effective mobility improvement is preserved. The top and side low-field mobilities ( mutop and muside, respectively) were extracted, showing + 90% mobility improvement at the sides (mutop = 125 cm2/V middots-1 and muside= 240 cm2/V middots-1).

We demonstrate for the first time 70 nm gate length TiN/HfO 2 pMOSFETs on 200 mm GeOI wafers, with excellent performance: I ON = 260 μA/μm and I OFF = 500 nA/μm @ V d = −1.0 V (without germanide). These performance are obtained using adapted counterdoping and pocket implants. We report the best CV / I vs. I OFF trade-off for Ge or GeOI devices: CV / I = 4.4 ps, I OFF = 500 nA/μm @ V d = −1 V. Moreover, based on fine electrical characterizations ( μ , D it , R access , etc.) at T = 77–300 K, in-depth analysis of both ON and OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I ON = 450 μA/μm, I OFF = 100 nA/μm @ V d = −1 V for L g = 70 nm.

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO 2 /TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances ( I ON , I OFF , transconductance, low field mobility, S , DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties ( μ h ∼ 250 cm 2 /V/s, I ON = 436 μA/μm for L G = 105 nm), and OFF current densities comparable or better than those reported in the literature.

In this paper, we report on reliability issues concerning the impact-ionization MOS (I-MOS). For the first time, the anomalously high off current in the planar I-MOS is studied owing to light-emission experiments. We show that a first breakdown occurs at the width borders of the device, followed by the theoretical volume breakdown. This result is intensively studied through 3D TCAD simulations. The results are correlated with electrical measurements. We finally propose and validate a degradation mechanism based on charge trapping.

Using C-V and G-V electrical modeling, we give insights on the atypical behavior of C-V characteristics with Ge substrates i.e. the low frequency behavior in strong inversion and the large bumps in the weak inversion region. The modeling of the strong inversion region reveals that a small density of bulk defects - in the range of 10^1^5-10^1^6.cm^-^3 - can explain the low frequency behavior of the C-Vs. The modeling of the depletion region takes into account the specific properties of germanium, especially the fast minority carrier response. It demonstrates that considering the occupation of interface defects by minority carriers is essential to explain the weak inversion bumps. This study also clearly shows that common D"i"t extraction techniques using C-V and G-V measurement on Si structures are no longer applicable for germanium.

Drift diffusion phenomena limits the subthreshold slope of conventional MOSFET to 60 mV/dec at room temperature. This paper deals with a new type of device, the Impact Ionization MOS (IMOS), which exhibits subthreshold slopes down to a few mV/dec. The electrical results of the fabricated IMOS are analysed and the scalability of this device is investigated thanks to TCAD simulations. The scaling of the dimensions allows a drastic reduction of the supply voltage and higher ON currents, but nanometer-large IMOS exhibit higher OFF current too due to Band-to-Band Tunnelling.

International audience; Stress engineering is a powerful tool to enhance nanoscale device performances. In this study we developed a methodology of 14nm strained pMOS FDSOI device mechanical simulation in order to carefully evaluate different stress effects on device performances. Mechanical simulation results are presented for different process solutions, such as Gate-First (GF) and Gate-Last (GL) processes but also for variation of germanium contents in source/drain and channel regions.

Tunnel FETs (TFET) are promising candidates for integration in logic circuits at very low supply voltages. We report here a SPICE compact model that describes all regimes of the TFET transistor. The current contribution from source and drain sides is described by an original set of equations including the electrostatic behavior and the effect of superlinear onset. Finally, this model is implemented using Verilog-A language and compared with TCAD simulations.

session 4: Steep slope devices; International audience; We report the fabrication and the characterization of Tunnel FETs fabricated on SiGe-On-Insulator with a High K Metal Gate (HKMG) CMOS process. The beneficial impact of low band gap SiGe channel on ID(VG) characteristics is presented and analyzed: compressive Si0.75Ge0.25 enables to increase by a factor of 20 the saturation currents, even at small gate length (LG=50nm). This large gain is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels).

We demonstrate the fabrication of strained Si-On-Insulator (sSOI) using a relaxation process of a compressive SiGe layer on SOI, and the transfer of lattice parameter from the relaxed SiGe to the Si layer. This process is based on a partial amorphization and recrystallization of the SiGe/Si stack. We used HRXRD (High Resolution X-Ray Diffraction) and TEM (Transmission Electron Microscopy) to characterize the microstructure of the layers. Strain and Stress evolutions throughout the process were determined using Raman spectroscopy and wafer bow measurements. Using a stack of 40 nm Si 0 . 7 Ge 0 . 3 on 9 nm Si, we obtained tensile Si layer having a stress of + 1.6 GPa which corresponds to a 80% lattice parameter transfer from SiGe to Si.

In this paper, we study the ambipolar tunneling signature from the output characteristics of TFETs featuring Si 0.8 Ge 0.2 homojunctions, which we compare to those measured on conventional MOSFETs and Schottky Barrier FETs. The difference with the former is immediate since a single TFET can display a transistor effect under both pull-up (nTFET) and pulldown (pTFET) biasing conditions. This is however a property shared with SBFETs, in which injection occurs via tunneling through a single carrier Schottky Barrier instead of band-to-band tunneling. Without requiring quantitative considerations on the current levels or transfer characteristics, we find that simply performing the same dual I d -V ds electrical tests while voluntarily "swapping" the S/D terminals unequivocally characterizes TFET operation, even compared to asymmetrically doped SBFETs.

Impact ionization MOSFET (IMOS) is a device that enables to reach subthreshold slopes as small as 5 mV/dec. This device has an asymmetric doping profile, and only a fraction of the channel is covered by the gate. In the first part of this paper, the purpose is to investigate the impact of some geometrical parameters on the IMOS performance: the gate length, the intrinsic length, and the Si film thickness. This study simulates a p-IMOS device on silicon-on-insulator using ATLAS. It is pointed out that the increase of the ratio LG/LIN allows a drop of the bias voltage, but involves a degradation of the subthreshold slope. A thin Si film improves the overall device performance. In the second part, the performance of an IMOS-based inverter is investigated, and for the first time an IMOS ring oscillator is simulated

Linear scaling CMOS has encountered many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described.