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3D integration so far has often been investigated through a face to face point of view: the top die FEOL is in front of bottom die FEOL. This allows a dense connectivity between both dies, but TSV are mandatory on the bottom die for each external exchange. Another flow chart, which main application is identified as the Wide I/O, is “face to back”: the FEOL of the top die faces to the back side of the bottom dies. To communicate between top & bottom, interconnections then TSVs are needed. Advantage is that the bottom die, for Wide I/O the logic dies, faces directly to the board allowing a rapid communication with external. Also, the Wide I/O interface delivers high bandwidth at relatively low power consumption level. The objective of this paper is to show latest integration at Leti, both on 200mm & 300mm wafers, using face to back integration. If we compare both flow charts, using via middle technology, the main challenge consists of the temporary bonding. The temporary adhesive needs to be at least 50 μm thick, even more depending on staking technology on board, and in presence of the macro connection. The choice of the adhesive is crucial for the final stability of the stack during back side process and also during debonding, even more on 300mm wafers. Technical developments are introduced in the paper. A specific focus is done on temporary adhesive & the associated thermal stability of the stack. Impact of the temporary bonding on copper pillar is evaluated. Assembly of best processes for a full integration on daisy chain wafers, both 200 & 300 wafers is described. Finally, a comparison of electrical datas (resistance, capacitance, isolation) for both wafer diameters is given. Morphological characterization finalizes this first integration and leads to further potential improvements.

In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296 mV@Vdd 1.1 V.

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple high-k/metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well suited for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk 45 nm technology in terms of variability and noise. A 0.499 μm2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1 V.

Charging phenomena is one of the main problems faced in ion implantation. Anti-charging system such as plasma flood gun (PFG) are currently running on high current and medium current implanters to reduce potential charging damage on device structures. However, in a conventional production line, high energy implantation steps are still often used without any charge compensation technique. Faced with micro-arcing defects detected after Well implantation steps on production lots, we have clearly demonstrated that the defectivity issue was eradicated by enabling the PFG system on the VIISta3000 high energy implanter. In addition we have investigated charging as a function of PFG properties by plasma damage monitoring (PDM) and proved that voltages developed on oxidized wafers processed on the VIISta3000 were not insignificant.

We study the effects of a strained contact etch stop layer (CESL) on fully depleted (FD) silicon-on-insulator (SOI) devices with ultra thin silicon channels. As expected from extensive simulation analysis, the electrical results demonstrate that in spite of the raised source/drain architecture, the stress is effectively transferred from the liner into the underlying channel. Using a tensile liner for the n-type metal–oxide–semiconductor field effect transistor (nMOS) and a compressive liner for the p-type metal–oxide–semiconductor field effect transistor (pMOS), transistor performance enhancements of 10% and 17%, respectively, were obtained. Moreover, with a tensile (/compressive) liner, tensile (/compressive) edge effects become dominant for short devices whereas the stress becomes less tensile (/compressive) for longer devices. Indeed, the balance between these two contributions and the strain level in the channel are highly dependent on geometrical parameters (W, Lgate).

We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.

In this paper, the interaction observed in PMOS transistor between the boron lightly doped drain (LDD) extensions and the spacer oxide and nitride dielectrics have been studied, with a simple experimental methodology. Low thermal budget oxide obtained by sub-atmospheric chemical vapor deposition (SACVD) and nitride deposited by plasma process have been evaluated as spacer layers. The influence of the oxide liner hydrogen content is shown to be critical for the p type shallow junction. Indeed, during the activation anneal, hydrogen content increases the boron out diffusion from the extension into the oxide liner and yield to a significant dose loss in this area. Nitride porosity has also been studied. A lower boron dose loss is observed with a porous layer because hydrogen can degas out significantly from the oxide, during anneal, through the porous nitride film. These results confirm the model of boron out diffusion based on oxide hydrogen content proposed by Kohli. Finally, a boron diffusion mechanism driven by chemistry and enhanced by hydrogen defects is proposed.

Classical beam line ion implantation is limited to low energies and cannot achieve P+/N junctions requested for Compared to conventional beam line ion implantation limited to a minimum energy implantation of 200 eV, plasma immersion ion implantation (PIII) is an emerging technique to get ultimate shallow profiles (as-implanted) due to no lower limitation of energy and high dose rate. On the another hand, laser thermal processing (LTP) allows to obtain very shallow junction with no TED, abrupt profile and activated depth control. In this paper, we show the implementation of the BF3 PIII associated with the LTP. Ions from BF 3 + plasma have been implanted in 200 mm n-type silicon wafers with energies from 100 eV to 1 keV and doses from 3E14 to 5E15 at/cm2 using PULSION® (IBS PIII prototype). Then, wafers have been annealed using SOPRA VEL 15 XeCl excimer lasers (l = 308 nm, 200 ns, 15 J/pulse) with energy density from 1 to 2.5 J/cm2 and 1, 3 or 10 shots. The samples have been characterized at CEA LETI by secondary ion mass spectrometry (SIMS) combined with four points probe sheet resistance measurements.

The future CMOS generations for microelectronics will require advanced doping techniques capable to realize ultra-shallow, highly-doped junctions with abrupt profiles. Recent experiments have shown the potential capabilities of laser processing of Ultra Shallow Junctions (USJ). According to the International Technology Roadmap for Semiconductors, two laser processes are able to reach ultimate predictions: laser thermal processing or annealing (LTP or LTA) and Gas Immersion Laser Doping (GILD). Both processes are based on rapid melting/solidification of the substrate. During solidification, the liquid silicon, which c ontains the dopants, is formed epitaxia lly from the underlying crystalline silicon. In the case of laser thermal annealing dopants are implanted before laser processing. GILD skips the ion-implantation step: in this case dopants are chemisorbed on the Si surface before the laser shot. The dopants are then incorporated and activated during the laser proce ss. Activation is limited to the liquid layer an d this chemisorption/laser shot cycle can be repeated until the desired concentration is reached. In this paper, we investigate the possibilities and limitations of the GILD technique for two different substrat es: silicon bulk and SOI. We also show so me laser doping applications for the fabrication of micro and nanoresonators , widely used in the MEMS Industry. Keywords: laser doping, ultra shallow junctions, impl antation, micro resonator, MEMS, LTP, GILD.

Semiconductor doping is a critical step in microelectronic device fabrication. Particularly, ultra-shallow junction formation for the CMOS 45-nm node is today intensively studied. Laser thermal processing (LTP) has already shown potentiality to achieve abrupt and ultra-shallow junctions, with a very low resistivity. However, the laser process has to be integrated in the conventional process flow of a real CMOS device fabrication. Therefore, the laser treatment needs to preserve the integrity of the different irradiated structures like transistor gates. Optical coatings, including reflective and anti-reflective coatings, can be used to protect the structures and to control the lateral diffusion of the dopants. In this work, we have studied different optical coatings (different materials and thicknesses) irradiated by a long pulse SOPRA VEL 15 excimer laser (200 ns–15 J). Junctions have been characterized by 4-point probe, in situ reflectivity, UV photometry and secondary ion mass spectroscopy. The efficiency and the integrity of the different coatings have been studied for different laser irradiation conditions in solid and molten phases. The results show that a proper optical coating optimizes the coupling of the deposited laser energy and is promising for improving the integration of the laser activation process of future CMOS junctions.

A new automated metrology tool using infrared spectroscopic ellipsometry is presented. After a description of the instrument with special attention on the spot size, the instrument specifications are described and one application of the technique related to the IC technology is presented. We show that physical and electrical information on Ultra Shallow Junction formed by Excimer Laser annealing for the sub 100 nm node on silicon on insulator (SOI) and on bulk silicon can be obtained independently. We compare these results with conventional techniques like four points probe and secondary ion mass spectroscopy (SIMS) and show a very good agreement.

According to the International Technology Roadmap for Semiconductors (ITRS), source and drain extensions thickness for 65 nm and below technology nodes MOSFET lead to a major challenge. Rapid thermal processing (RTP) tools reach the limit of their physical abilities in term of temperature cycle and pulsed laser thermal processing (LTP) tool arise as a major potential candidates to solve the fundamental problem of ultra-shallow junction (USJ) activation. LTP experiments have been performed with two different XeCl excimer lasers ( λ =308 nm) with different pulse characteristics (20 and 200 ns). We examine the influence of the pulse duration on LTP of B + (with and without Ge + pre-amorphization) implanted silicon samples on the basis of real-time optical monitoring of the laser induced process, four-point probe resistivity measurements and secondary ion mass spectroscopy (SIMS) depth profiles. Experimental results are compared to model calculations for both laser pulses. The activated dopant dose, junction depth and sheet resistance, as a function of the laser fluence and shot number for both lasers, confirm the relevance and efficiency of laser processing to realize ultra-shallow and highly doped junctions required for the future CMOS generations. Influence of the pulse duration on the USJ formation process is also discussed. In particular, we show the capabilities of the 200 ns pulse to activate B in Si without melting the Si doped layer.

Gas immersion laser doping (GILD) is a very attractive technique to realize the ultra-shallow and highly doped junctions required by the International Technology Roadmap for Semiconductors (ITRS) for future CMOS technologies. In the present work, gaseous dopant precursors (BCl 3 ) are chemisorbed on the Si surface, and partially incorporated during the melting/recrystallisation of the Si top layer induced by an UV laser pulse ( λ =308 nm, pulse duration ≈25 ns). The resulting thickness and dopant concentration of the doped layer depend on the laser energy density and the number of chemisorption/laser-induced incorporation cycles (up to 200). GILD processed junctions are box-like and exhibit depths ranging from 14 nm to 65 nm, with sheet resistances ranging from ≈110 to 20 Ω/□ (respectively), dopant concentrations well above the B solubility limit in Si (up to 3×10 21 at/cm 3 ) at local thermodynamic equilibrium (LTE) and abruptness of 5–2 nm/decade. Moreover, in situ optical characterization shows the GILD technique capabilities to realize the sub-10 nm thick shallow junctions needed for the sub-40 nm node ITRS predictions.

Cette etude concerne les techniques de recuit laser (LTP) et de dopage laser direct (GILD) de jonctions ultra-minces, necessaires a la fabrication des composants microelectroniques du futur (generations CMOS sub 0,1 μm). Des jonctions de 20 a 80 nm sont realisees a l'aide d'un laser a excimeres. Le procede est suivi en temps reel grâce a l'analyse de la reflectivite transitoire a 675 nm. L'evolution de l'activation des dopants est ensuite caracterisee par spectroscopie IR (FTIR). Les resultats obtenus permettent de caracteriser les jonctions en termes d'epaisseur dopees, concentration et resistivite. Une comparaison avec des caracterisations classiques (mesures electriques de resistivite, profils SIMS) permet de valider ces mesures et de mettre en evidence l'interet des techniques optiques pour la caracterisation in-situ et ex-situ des couches minces dopees realisees par laser.

In the last few years, laser thermal processing (LTP) has become a potential solution for sub-0.1 μm technology requirements, as focused by the international technology roadmap for semiconductors (ITRS). This paper presents a numerical simulation of the propagation of the melting front and regrowth of Si-based structures during excimer (XeCl-308 nm) laser irradiation. The influence of the pulse duration is highlighted in the simulation and compared with experiments. Two different types of XeCl lasers with different pulse durations have been used for the experiments in order to validate the model (SOPRA VEL 15, 200 ns, 15 J and Compex Lambda Physik, 20 ns, 200 mJ). The comparison between the simulation and the experimental results has been carried out using results from in situ reflectance measurements (transient reflectivity), secondary ion mass spectroscopy, spreading resistance profiles and four-point probes. The different implantation conditions used for this study were B + or BF 2 + implanted Si wafers, with or without Ge + pre-amorphization. Both experimental and simulation results show the potentiality of the LTP annealing technique for realization of ultra shallow junction under 0.1 μm.

In the tokamak Tore Supra, when a poloidally and toroidally localized limiter, called a modular limiter, is introduced into the lower part of the scrape-off layer, density fluctuations located in the vicinity of this limiter present a specific feature with the appearance of a new spectral pattern in the associated frequency spectrum. This leads to a strong up-down asymmetry observed in both the plasma edge and the plasma outer core, with a maximum level of turbulence at the bottom of the plasma. The observed asymmetry characteristics show that magnetic connection lengths play a critical role here and that the limiter configuration has some effect on the outer core turbulence.

In Tore Supra, density fluctuations near to the plasma edge present up-down asymmetries which increase with the edge safety factor, weakly depend on density and reverse with the plasma current direction. The strongest asymmetries are observed in the particular case where the plasma is leaning on the lower limiter close to the measurement chord, with a connection length along the magnetic field line to the lower measurement region of the order of 0.6 m. For strong asymmetries, top and bottom k-spectra have different slopes. Possible theoretical explanations for these asymmetries are briefly discussed.

For 0.25 @mm Non Volatile Technology (NVM) we developped a SiON inorganic BARC layer in a standard P5000 Applied Materials PECVD reactor &{1&}. One of the major drawbacks with SiON is the interaction between nitride and DUV resists: we observed footing with UV5 Shipley resist. A simple solution is to have a surface treatment before lithography. Unfortunatly surface treatment can disturb optical properties of the material because ARC thickness and optical constants controls have to be very accurate. In this paper we describe the surface treatment validation sequence:- effect of the treatment on the resist footing - influence of the surface treatment on resist swing curve - efficiency of the treatment on the resist line's crossing topographic step technology - time stability of the surface treatment - influence of rework and stripping on the treatment. Finally we demonstrate the feasability of 0.25 @mm NVM lithography with inorganic BARC

On Tore Supra, the frequency spectra of the turbulent fluctuations often have two peaks centred on some positive and negative values. These two peaks correspond to a poloidal motion of the electrons in opposite directions. In this paper, a criterion is elaborated which allows us to distinguish, in time, the density fluctuations convected in the parallel direction from those in the anti-parallel direction with respect to the analysing wavevector. Two signals are thus extracted out of one. The validity of our model is experimentally checked by comparing the auto-correlation coefficients and the frequency spectra computed for the whole and the separated signals. Consequently, the frequency spectrum is studied in detail as a function of the analysing wavenumber leading to an accurate determination of some plasma properties.

It is believed that radial anomalous transport in tokamaks is caused by plasma turbulence. Using infra-red laser scattering techniques on the Tore Supra tokamak, statistical properties of the density fluctuations are studied as a function of the scales in ohmic as well as additional heating regimes using the lower hybrid or the ion cyclotron frequencies. The probability distributions are compared to a Gaussian in order to estimate the role of intermittency which is found to be negligible. The temporal behaviour of the three-dimensional spectrum is thoroughly discussed; its multifractal character is reflected in the singularity spectrum. The auto-correlation coefficient is shown to reflect a short-time coherence of the dissipative structures as well as their long-time incoherence and statistical independence. We also put forward the existence of fluctuations transfer between two distinct but close wavenumbers. A rather clearer image is thus obtained about the way energy is transferred through the turbulent scales.

A parametric experimental study of fluctuations has been performed in L-mode plasmas during steady-state phases in Tore Supra. Simultaneous measurements of density and magnetic fluctuations in the gradient region of the discharge show that both components are strong functions of the local electron temperature decreasing lengths. The wavenumber spectrum of density fluctuations is obtained with the scattering diagnostic both in the bulk and at the edge of the discharge. In the bulk, in the L-mode compared to ohmic plasmas, the k spectrum increases below and is globally shifted towards low k values. At the edge (r/a > 0.9) an increase on all k values is observed. At r/a = 0.5, the level of both types of fluctuations is found to be linearly correlated with the local heat diffusivity . The heat flux ratio advected by electrostatic eddies in the bulk of the discharge is estimated by using fluctuation measurements and generic predictions for the parametric dependency of the thermal flux. The calculated level of density fluctuation necessary to account for the heat transport at midradius is found to be compatible with values measured in other tokamaks. It is also found that the heat flux ratio behaviour conducted by electrostatic fluctuations is compatible with most of the experimental heat flux ratio behaviour in the plasma core (0.4 < r/a < 0.6). This property does not hold at the edge of the plasma (r/a = 0.7). The similar parametric dependency of magnetic and density fluctuation level does not allow one to make a clear statement about their relative importance in the transport process and suggests that they could be coupled.

Wafer level molding is an important process step in the chip on wafer approach and seems currently required in stacking first process flow. Thermo-mechanical properties of molding material has to be controlled to limit stress induce by CTE mismatch with silicon wafer and also to assure planarization and protection functions. 2D and 3D finite element simulations have been performed to evaluate strain and stress impact at wafer level of material properties of silicone based and epoxy based molding compounds. Impacts of Si interposer thickness, design and chips arrangement on wafer warpage are presented and compared with experimental results.

Some 3D interconnects technologies are reviewed and discussed in this paper with respect to emerging 3D applications. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, the very fine pitch below 10μm will be mandatory for 3DIC and many options like cu-cu bonding or μ-tubes are in the race. Specific interconnects for RF/mm-waves and low volume electronics devices are also discussed with relevant examples.

This paper presents a comparison between electrical measurements, which are carried out with embedded in-situ sensors, and thermal numerical simulations. The objectives of this study are firstly to calibrate the Finite Element model by comparing the measurement results with those from simulations through a Design Of Experiments (DOE), and then to provide thermal recommendations on the studied parameters thanks to the calibrated numerical model. The primary objective of the DOE is to quantify the sensitivity of modeling parameters. Results show a strong influence of the silicon thickness, the convective heat transfer coefficient of the bottom surface, the thickness of the thermal insulation and the position of the hot spots relative to the sensors. The boundary conditions, particularly the heat transfer coefficient are also identified as significant parameters. Once the main factor set determined, the second objective of this study is to weight quantitatively the influence of key parameters. Finally, by providing a numerical and experimental comparison, this paper provides validated values of boundary conditions to be applied in the numerical simulations. These are considered to be the most difficult to obtain, while they have a huge influence on the simulation results, and this work allows to provide reliable thermal recommendations on designs to manage self-heating challenges.

3D integration, also referred as “More than Moore” approach is considered as the most attractive alternative to “More Moore” concept in order to increase circuit functionalities and performances while keeping reasonable cost of integrated devices. This technology has been widely presented and discussed during last years and is now available on several world wide integration platforms. Major part of the work done in recent years was focused on the three challenges to be overcome to allow manufacturing of 3D technology: design, process integration and tests. This was presented [1] as the availability of a complete toolbox including the design kit definition, the development and maturity increasing of the required process modules such as TSV, Wafer bonding and debonding, back side contact, both side interconnects and the definition of functional and reliability tests. This toolbox is dedicated to the construction of specific process flows and designs depending on the targeted applications. These applications, in the 3D integration world, are very flexible going from the passive and active interposers to memory on logic or logic on logic partitioning as well as stackable processors. Today, the different process modules are at a sufficient maturity state to allow the realization of demonstrators for all types of integration schemes. Depending on the type of integration flow and requested device, challenges to perform this demonstrator can come from the process integration itself but also from the need of specific equipment toolset. Base wafers already containing devices for 3D demonstrator can come from various site and be of different size. The demonstrator can be fully realized from bulk silicon as it is the case for an interposer or the 3D part of the device, only, will have to be developed which will be the case for heterogeneous integration. For this, a new 300 mm pilot line was built in Leti in addition to the 200 mm one and was designed to be compatible with manufacturing lines. These facilities are today allowing the realization of 300 mm 3D demonstrators. Results of these prototypes and the challenges overcome for integration are discussed in this paper.

Three-dimensional (3D) stacked IC technologies have become a central topic over the past few years, and start to become reality with the introduction of 3D devices in commercialization. Among the technical challenges raised by this technology, thin wafer handling remains one of the most challenging. A large number of publications have focused on this process since several years to present the performances of the different competitors. The goal of this paper is to discuss the 300mm interposer creation process using 2 of the most spread temporary bonding techniques: ZoneBOND™ and WSS (Wafer Support System). The comparison will be achieved during the different process steps considering 50μm or 80μm thick silicon interposers. The comparison will be done considering the 2 major challenges of temporary bonding integration: interposer flatness control and stability during the backside process. Finally this work has enabled us to identify the drawbacks and advantages of each technique for 3D integration.

This study focuses on alternative technologies for fine pitch 3D interconnect. These technologies are: μ-inserts (insertion of a nickel cylinder in Aluminium pad), μ-tubes (insertion of a hard tube in Aluminium pad), Transient Liquid Phase (TLP) bonding (whole solder reacts to form intermetallic compound) and copper direct bonding. In the first part the process flow is described. Then electrical performances are presented, including a comparison of the Kelvin resistance for each technology. The next part presents reliability considerations, where the failure modes and the weaknesses of each interconnect technologies are described. The mechanical impact of insertion technologies is also studied.

The results of theoretical and experimental studies on excitation of drift waves in a tokamak plasma under the conditions of experiments on lower‐hybrid (LH) plasma heating and current drive are presented. It is shown that for sufficiently strong LH pump levels the main effect resulting in the drift wave excitation is the LH wave modulational instability. It is found that the modulational excitation of long‐wavelength drift oscillations (with the wavelengths exceeding the length of the LH pump wave) is described by a dispersion equation similar to the equation for the usual hydrodynamical beam instability. This allows us to treat the excitation of the long‐wavelength drift waves as modulational excitation by a beam of the LH waves. The theoretical results obtained are compared with the data of the tokamak Tore Supra [Proceedings of the 12th International Conference on Plasma Physics and Controlled Nuclear Fusion, Nice, 1988 (International Atomic Energy Agency, Vienna, 1989), p. 9] experiment. Qualitative accordance of the theoretical and experimental results is demonstrated.

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

The purpose of this paper is to investigate integration results of 300mm silicon wafers thinned at 80μm down to 50μm using the innovative temporary ZoneBOND™ technology to handle the device during the process flow. A focus on the coating/bonding and thinning process of 80μm and 50μm thick silicon interposers is made. A tape selection study enabled us to identify two separation tapes compatible with varying interposer backside topology as well as the adhesive cleaning chemistries. After the validation of these fundamental processes, we created fully-functional interposers presenting 10×80 μm or 6Χ55μm TSVs. We measured the TTV and deformation through all the thinning and the backside processes. No significant TTV difference has been observed and all steps whatever the interposer type successfully pass the integration process. Finally, in order to increase the process window of the dielectric and TSV CMP, different oxide deposits are tested on 300mm temporary bondings thinned at 80μm or 50μm. This study confirmed that the dielectric deposition process remains one of the most challenging steps of the backside process. It has been observed that the use of hard mask type deposition process does not damage temporary bonding interface whereas TEOS type deposits at 200°C initiate damage at bonding edges which are more significant for 50μm interposer and thicker deposition layers. This work concludes on the process limitations with the use of ZoneBOND™ technology.

The level of density fluctuations is shown to decrease during ergodic divertor operation in Tore Supra. This decrease of the turbulence is correlated with the onset of a temperature pedestal and a local improvement of the confinement. This pedestal is located close to the electric shear layer, i.e. within a narrow region between the plasma core and the ergodic layer. The onset of such a pedestal explains why the central electron temperature is not changed when the ergodic divertor is switched on, in spite of an ergodic zone where the temperature is low

The different reflectometry methods currently used for the determination of electron density profiles of fusion plasmas suffer serious limitations due mainly to plasma fluctuations and to parasitic reflections in the transmission waveguides. An advanced method, based on pulse compression radar techniques, can be applied to overcome these limitations. This paper reports two series of results obtained at JET, which for the first time validate the pulse compression method for reflectometry on thermonuclear plasmas. The first results are for a reflector positioned a short distance beyond the end of a long, complex and oversized waveguide. The same waveguide is used for transmission and reception, inducing many parasitic reflections. The second series of results are from measurements on JET plasmas, using different waveguide configurations. Results both with the reflector and the plasma show that multiple reflections within the transmission line can be eliminated by a correction technique in the signal analysis procedure. A precision of typically 1 cm can be obtained for the measured position of the reflector, or the plasma cutoff layer, with only 20-50 frequency steps. With the fast frequency synthesizers currently available, the complete measurement could be made in 2-5 mu s, thereby freezing plasma fluctuations due to MHD and most of the microturbulence.

The characteristics of ergodic divertor (ED) deuterium plasmas in the Tore Supra tokamak are discussed. The divertor volume is a relatively well limited region between the ED modules and ρ = τ/a equivalent to 0.8. The core (ρ ≤ 0.8) plasma confinement is not degraded by the presence of the ED (by comparison with similar limiter, non-ED plasmas): the electron density and temperature profiles are not modified. The ED configuration compares well with a classical X point divertor: intrinsic impurities are screened out, the power load is deflected to dedicated surfaces, and density control through particle pumping is possible. Up to 5.5 MW of ion cyclotron resonance power and 3 MW of lower hybrid power have been successfully used, power exhaust being mainly by radiation (80%)

Several discharges have been analysed in Tore Supra in order to improve the understanding of anomalous transport. In ohmic discharges, it has been shown that both particle and heat diffusion coefficients improve with increasing density, then saturate. The level of edge density fluctuations behave in the same way. In the presence of additional heating, the bulk and the edge turbulences behave differently. The level of edge density fluctuations remains constant in most discharges with additional heating (up to 8 MW). In practice, it only depends on edge conditions. On the contrary, the level of core magnetic fluctuations increases systematically with any additional power. Finally, a lowering of the level of the edge density fluctuations has been observed when using the Tore Supra ergodic divertor. This improvement is accompanied by the onset of a temperature pedestal between the plasma bulk and the ergodic layer. This explains why the global confinement remains unchanged in presence of the ergodic divertor in spite of the reduced radius of the last closed magnetic surface.

International audience; Tore Supra routinely addresses the physics and technology of very long-duration plasma discharges, thus bringing precious information on critical issues of long pulse operation of ITER. A new ITER relevant lower hybrid current drive (LHCD) launcher has allowed coupling to the plasma a power level of 2.7 MW for 78 s, corresponding to a power density close to the design value foreseen for an ITER LHCD system. In accordance with the expectations, long distance (10 cm) power coupling has been obtained. Successive stationary states of the plasma current pro le have been controlled in real-time featuring (i) control of sawteeth with varying plasma parameters, (ii) obtaining and sustaining a `hot core' plasma regime, (iii) recovery from a voluntarily triggered deleterious magnetohydrodynamic regime. The scrape-off layer (SOL) parameters and power deposition have been documented during L-mode ramp-up phase, a crucial point for ITER before the X-point formation. Disruption mitigation studies have been conducted with massive gas injection, evidencing the difference between He and Ar and the possible role of the q = 2 surface in limiting the gas penetration. ICRF assisted wall conditioning in the presence of magnetic eld has been investigated, culminating in the demonstration that this conditioning scheme allows one to recover normal operation after disruptions. The effect of the magnetic eld ripple on the intrinsic plasma rotation has been studied, showing the competition between turbulent transport processes and ripple toroidal friction. During dedicated dimensionless experiments, the effect of varying the collisionality on turbulence wavenumber spectra has been documented, giving new insight into the turbulence mechanism. Turbulence measurements have also allowed quantitatively comparing experimental results with predictions by 5D gyrokinetic codes: numerical results simultaneously match the magnitude of effective heat diffusivity, rms values of density uctuations and wavenumber spectra. A clear correlation between electron temperature gradient and impurity transport in the very core of the plasma has been observed, strongly suggesting the existence of a threshold above which transport is dominated by turbulent electron modes. Dynamics of edge turbulent uctuations has been studied by correlating data from fast imaging cameras and Langmuir probes, yielding a coherent picture of transport processes involved in the SOL.

A collective infra-red laser scattering diagnostic has been installed on the TORE SUPRA tokamak for the measurement of plasma density fluctuations. For the range of wavenumbers explored (3-15 cm-1), the scattering angles are very weak ( approximately 1 mrad). Consequently, the scattering signals are averaged along the whole observation chord, resulting in poor longitudinal spatial localization. By virtue of the pitch angle variation of the magnetic field lines in the tokamak, and of the perpendicularity of the turbulence wavevector to these field lines, it has been possible to obtain partial spatial resolution along the direction of the beam. Good agreement between the experimental and theoretical angular resolution of the diagnostic as well as the results of cross-correlation performed on the signals obtained by two simultaneous probing beams also justify this novel concept.

Results on confinement and turbulence from a set of Ohmic discharges in TORE SUPRA are discussed. Attention is focused on the saturation of the energy confinement time and it is emphasized that this saturation can be explained by a saturation of the electron heat diffusivity. The ion behaviour is indeed governed by dilution and equipartition effects. Although the ion heat transport is never neoclassical, there is no enhanced degradation at saturation. This behaviour is confirmed by turbulence measurements using CO2 laser coherent scattering. The level of density fluctuations follows the electron heat diffusivity variations with the average density. Waves propagating in the ion diamagnetic direction are always present in turbulence frequency spectra. Thus, the saturation cannot be explained by the onset of an ion turbulence. The existence of ion turbulence in the edge at all densities cannot be excluded. However, this ion feature in scattering spectra could be explained by a Doppler shift associated with an inversion point of the radial electric field at the edge

Magnetized plasmas occurring in nature as well as in fusion laboratories are often irregularly shaken by magnetic field fluctuations. The so-called 'coherent scattering' of electromagnetic waves from nonuniform, irregularly moving plasmas is investigated in the case where the scattering wavelength is large compared to the Debye length, but of the order of the irregularities correlation length. The scattered signal frequency spectrum is shown to be a transform of the plasma motion statistical 'characteristics'. When the scattering wavelength is larger than the plasma motion correlation length, the frequency spectrum is shown to be of a Lorentzian shape, with a frequency width that provides a direct measurement of the cross-B particle diffusion coefficient. This is illustrated by two series of experimental results: radar coherent backscattering observations of the auroral plasma, and far infrared scattering from tokamak fusion plasma. Radar coherent backscattering shows the transition from Gauss to Lorentz scattered frequency spectra. In infrared laser coherent scattering experiments from the Tore-Supra tokamak, a particular frequency line is observed to present a Lorentzian shape, that directly provides an electron cross-field diffusion coefficient. This diffusion coefficient agrees with the electron heat conductivity coefficient that is obtained from the observation of temperature profiles and energy balance.

A collective laser light scattering diagnostic ALTAIR (a french acronym for local analysis of anomalous transport using infrared light), using a CO2 laser beam (λ=10.6 μm) has been realized to measure plasma density fluctuations in the TORE SUPRA tokamak. This article describes in detail the optical setup, the signal processing, acquisition, and control systems required for this experiment. As the density fluctuations propagating in tokamaks have small wave numbers and require small scattering angles, such scattering experiments are considered as having no resolution along the beam. However, taking advantage of the pitch angle variation of the magnetic field lines around the magnetic axis along a vertical chord, it has been possible to obtain partial spatial localization of the scattering volume by rotating the direction of the analyzed wave vector in a horizontal plane. Heterodyne detection is used to determine the fluctuations propagation direction. The experiment has been tested on acoustic waves and t...

For the first time we demonstrate the CMOS integration of undoped fully-depleted Ultra Thin Body and BOX devices (UTB2) with (110)/(100) substrate crystal orientation for pFET and nFET respectively. For this, we used an original 3D-folded Bulk+/Silicon-On-Nothing (SON) process on DSB substrate. Resulting multi-surface orientations devices are studied.

The main results of the Tore Supra experimental programme in the years 2007–2008 are reported. They document significant progress achieved in the domain of steady-state tokamak research, as well as in more general issues relevant for ITER and for fusion physics research. Three areas are covered: ITER relevant technology developments and tests in a real machine environment, tokamak operational issues for high power and long pulses, and fusion plasma physics. Results presented in this paper include test and validation of a new, load-resilient concept of ion cycotron resonance heating antenna and of an inspection robot operated under ultra-high vacuum and high temperature conditions; an extensive experimental campaign (5 h of plasma) aiming at deuterium inventory and carbon migration studies; real-time control of sawteeth by electron cyclotron current drive in the presence of fast ion tails; ECRH-assisted plasma start-up studies; dimensionless scalings of transport and turbulence; transport experiments using active perturbation methods; resistive and fast-particle driven MHD studies. The potential role of Tore Supra in the worldwide fusion programme before the start of ITER operation is also discussed.

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide u ltra t hin b ody and b uried oxide (UTB 2 ) devices with improved drive current I on for a given designed footprint W design when scaling the device width . We compare the fabrication and electrical behavior between 〈1 1 0〉 channel, i.e. 0°-rotated wafer, and 〈1 0 0〉 channel, i.e. 45°-rotated wafer, for the same (1 0 0) surface orientation.