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In this article, we have studied the impact of different doped hafnium oxides (X:HfO2) in ferroelectric field-effect transistors (FeFETs) based on 28-nm high-K metal gate (HKMG) and 12-nm fully depleted silicon-on-insulator (FDSOI) technology. The introduction of different elements through appropriate doping enables the stabilization of a higher symmetrical phase in HfO2 (cubic, tetragonal) and the final transition to the orthorhombic phase, which is the origin of ferroelectricity. The required concentration for this stabilization is different for different dopants, which in turn results in different ferroelectric parameters such as coercive electric field ( ${E}_{c}$ ) and remnant polarization ( ${P}_{r}$ ). These parameters impact the memory window and trap densities at or near the SiO2/X:HfO2 interface. The density-functional theory (DFT) calculations using the first-principle method also verify the above. The carriers’ trapping/de-trapping results in a change in the threshold voltage and endurance issues. A DFT and TCAD-based study has shown the reliability aspects of ferroelectric transistors due to different HfO2-dopants, which is necessary for ferroelectric material optimization for low-voltage logic and memory applications.

This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in the analog domain. The proposed architecture consists of a $64\times 64\,\,9$ T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight (4-bit) in a cycle, and an optimized 4-bit Flash ADC is used for converting the analog MAC into digital output. This brief achieves a throughput of 455 GOPS and an energy efficiency of 1012 TOPS/W at 222 MHz, maintaining a very high signal margin of 54 mV. The achieved inference accuracy is 98% for MNIST and 86% for the CIFAR-10 data set. This proposed work is implemented on a 28 nm CMOS Technology node at 0.9 V supply.

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage $(V_{\mathrm{ th}})$ of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ( $t$ ). A device-level approach for $V_{\mathrm{ th}}$ degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of $t$ . A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with $t$ to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.