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Summarization: In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations. Presented on: IEEE Transactions on Electron Devices

Summarization: High temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double-gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500ºC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs. Παρουσιάστηκε στο: Materials Science Forum

Summarization: The design of radiation-hard analog/mixed signal Integrated Circuits for high Total Ionizing Dose (TID) is a challenging task. Front-end electronics for the High-Luminosity Large Hadron Collider (HL-LHC) are expected to be exposed to doses exceeding 500 Mrad(SiO2). Using a recently developed TID-Process Design Kit (PDK) in 65 nm bulk CMOS, the present paper illustrates the design of micropower, current-mirror and folded cascode CMOS Operational Transconductance Amplifiers (OTAs) using moderate inversion techniques to favor insensitivity to high TID. Παρουσιάστηκε στο: 8th International Conference on Modern Circuits and Systems Technologies

Summarization: Frond-end electronics at the High Luminosity-Large Hadron Collider (HL-LHC) at CERN, will be exposed to ten-fold radiation doses. The use of enclosed gate (EG) MOSFETs of 65 nm Bulk CMOS process, is considered to be a viable solution in order to suppress performance degradation effects that occur after high TID exposure. The present paper presents a detailed analysis of the functionality of EG MOSFETs operating under high TID, taking into accountspecific layout characteristics. Παρουσιάστηκε στο: 26th International Conference "Mixed Design of Integrated Circuits and Systems"

Summarization: High doses of ionizing radiation drastically impair the electrical performance of CMOS technology. Enclosed gate layout remains an effective means to reduce this impact. Nevertheless, high total ionizing dose (TID) effects remain strong. The paper presents an effective approach to analytically model high TID effects in both NMOS and PMOS transistors with enclosed-gate layout in 65 nm commercial CMOS. Παρουσιάστηκε στο: 41st International Semiconductor Conference

In den letzten Jahrzehnten hat die Digitalisierung alle Bereiche des Lebens durchdrungen. Internet, Computer und Smart Devices sind nicht mehr wegzudenken. In der Produktion wird die Digitalisierung mit dem Schlagwort „Industrie 4.0“ beschrieben. Ziel ist hierbei die Vernetzung von Mensch, Maschine und Produkt zu einem Internet der Dinge, Dienste und Daten. Ein weiterer Trend ist ein gesunder Lebensstil sowie eine ausgewogene Work-Life-Integration. Besonders die Generation Y strebt nach einem fitten, starken Körper und einer gesunden Ernährung. Zahlreiche Workshops und Apps unterstützen diesen Trend. Im beruflichen Umfeld gestaltet sich dieser Lebensstil jedoch schwierig. „Warum diese beiden Trends also nicht verbinden!“, dachte sich das Unternehmen viastore SOFTWARE GmbH aus Stuttgart, „Arbeit, Fitness und Spaß an einem Arbeitsplatz“. Was sich für viele unvorstellbar anhört, wird im Rahmen des Forschungsprojektes „MyCPS“, in der Intralogistik umgesetzt. Ein handelsüblicher Fitness-Tracker stellt dem Warehouse-Management-System Vitaldaten wie Herzfrequenz oder ein Aktivitätsprotokoll zur Verfügung. Mithilfe dieser Daten können die auftretenden Beanspruchungen des Mitarbeiters in Relation zu seiner Tätigkeit gesetzt und somit Aspekte einer ergonomischen Arbeitsgestaltung bei gleichzeitiger Berücksichtigung der persönlichen Bedürfnisse der Mitarbeiter verwirklicht werden., aw&I Conference, Bd. 3 (2018): innteract2018

Summarization: The present work describes a novel charge-based compact model of the symmetric double-gate junction field effect transistor (DG JFET) for circuit simulation. The model is physics-based and addresses static and capacitive behavior of the JFET. The model covers all regions of device operation of the depletion mode JFET, relies only on physical and electrical parameters of the device, and includes short-channel effects. The model is validated with respect to TCAD simulation as well as with respect to measurements from JFETs. The model is implemented in SPICE circuit simulators using Verilog-A based code. Παρουσιάστηκε στο: 48th European Solid-State Device Research Conference

Summarization: Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID). In the present paper, geometrical scaling of key analog design parameters of MOS transistors irradiated at high TID is investigated. Experiments are carried out for TID of 100, 200 and up to 500 Mrad(SiO2) and at -30°C, 0°C, and 25°C. We find that parameters are least degraded at -30°C. However, short-channel NMOSTs show a significant degradation of slope factor, which is more severe at 0°C than at 25°C. In contrast, the slope factor in short-channel PMOSTs shows lowest sensitivity to high TID. Παρουσιάστηκε στο: 25th International Conference ""Mixed Design of Integrated Circuits and Systems""

Summarization: High doses of ionizing irradiation cause significant shifts in design parameters of standard bulk silicon CMOS. Analog performance of a commercial 65 nm CMOS technology is examined for standard and enclosed gate layouts, with Total Ionizing Dose (TID) up to 500 Mrad(SiO2). The paper provides insight into geometrical and bias dependence of key design parameters such as threshold voltage, DIBL, transconductance efficiency, slope factor, and intrinsic gain. A modeling approach for an efficient representation of saturation transfer characteristics under TID from weak through moderate and strong inversion and over channel length is discussed. Παρουσιάστηκε στο: IEEE International Conference on Microelectronic Test Structures