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To tolerate faults in Networks-on-Chip (NoC), routers are often disconnected from the NoC, which affects the system integrity. This is because cores connected to the disabled routers cannot be accessed from the network, resulting in loss of function and performance. We propose E-Rescuer , a technique offering a reconfigurable router architecture and a fault-tolerant routing algorithm. By taking advantage of bypassing channels, the reconfigurable router architecture maintains the connection between the cores and the network regardless of the router status. The routing algorithm allows the core to access the network when the local router is disabled.Our analysis and experiments show that the proposed technique provides 100% packet delivery in 100%, 92.56%, and 83.25% of patterns when 1, 2 and 3 routers are faulty, respectively. Moreover, the throughput increases up to 80%, 46% and 33% in comparison with FTLR, HiPFaR, and CoreRescuer, respectively.

It is known that maliciously configured Network-on-Chip routers can enable an attacker to launch different attacks inside a Multiprocessor System-on-Chip. A source authentication mechanism for router configuration packets can prevent such vulnerability. This ensures that a router is configured by the configuration packets sent only by a trusted configuration source. Conventional method like Secure Hash Algorithm-3 (SHA-3) can provide required source authentication in a router but with a router area overhead of 1355.25% compared to a normal router area. We propose eight source authentication mechanisms that can achieve similar level of security as SHA-3 for a router configuration perspective without causing significant area and power increase. Moreover, the processing time of our proposed techniques is 1/100th of SHA-3 implementation. Most of our proposed techniques use different timing channel watermarking methods to transfer source authentication data to the receiver router. We also propose the Individual packet-based stream authentication technique and combinations of this technique with timing channel watermarking techniques. It is shown that, among all of our proposed techniques, maximum router area increment required is 28.32% compared to a normal router.

The router as the main component of on-chip networks has a key role in making connections between the processing cores. Thus, regarding the unreliable silicon, preserving the routers in operational states has a great effect on the network performance. Among different units of a router, the input ports including the buffers have a high fault occurrence probability due to consuming a large portion of a router's area. This paper presents a fault tolerant router architecture which utilizes a new decoupled resource sharing approach for the input ports. The proposed architecture highly improves the overall reliability and network performance against multiple permanent faults in the input ports even incorporating a non-fault tolerant routing algorithm. Furthermore, the new resource sharing approach decreases the packet latencies while the faulty links exist in the network. The experimental results show that all improvements are achieved at the cost of a very low hardware overhead compared to the baseline router while the proposed router architecture reaches to greatest Silicon Protection Factor (SPF) as a metric compared to all previous designs.

The IPv6 Neighbor Discovery protocol specifies the maximum time allowed between sending unsolicited multicast Router Advertisements (RAs) from a router interface as well as the maximum router lifetime. It also allows the limits to be overridden by documents that are specific to the link layer. This document allows for overriding these values on a per-link basis. This document specifies updates to the IPv6 Neighbor Discovery Protocol (RFC 4861) to increase the maximum time allowed between sending unsolicited multicast RAs from a router interface as well as to increase the maximum router lifetime.

With the booming of Cloud Compute, OpenStack has been more widely used in Data Center, but in tradition deployment of OpenStack, the traffic must traverse network node to get routing decision. So the network node would be a bottle-neck due to the increasing amount of data flow. In order to solve this problem, this paper propose an extensible design, we create a internal virtual router in each compute node, the internal virtual router just can process the East-West traffic in lay2. With the help of distributed router, the East-West traffic can be delivered directly from the source hypervisor to the destination hypervisor, no longer need to traverse the router in network node to get routing decision, Therefore, North-South and East-West traffic don't impact each other anymore. North-South traffic enjoys all the bandwidth of router in network node exclusively, hence reduce the load of the network node. Experiment results show that OpenStack with distributed router has a much better performance evaluation than original OpenStack. This will dramatically increase the total bandwidth, and also bring other advantages.

International audience; Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underutilization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.

International audience; Network-on-Chip provides scalable communication in Systems-on-Chip with many Intellectual Property cores. Studies have shown that unutilized router buffers lead to significant network performance degradation. This work presents Roundabout, a new asynchronous router architecture with inherent and effective buffer utilization. Inspired by real-life multi-lane roundabouts, it consists of lanes shared by input and output ports. A prototype of Roundabout is evaluated using 45nm CMOS technology. The router is able to achieve a throughput of 465 Mflit/sec. It achieves a network saturation threshold of 129 Gbps on a 4x4 Mesh topology network. Roundabout performance, area and power results are competitive with existing synchronous and asynchronous solutions. It provides good topological tradeoffs for significantly improving network performance without corresponding area overhead.

Due to the problem of high hardware cost and low yield of the TSV in 3D NoC, the vertically partially connected 3D NoC with limit number of TSV has been researched widely. With respect to little research on micro-buffered router which is suitable for this topology and can further reduce hardware cost, a micro buffered router in vertically partially connected 3D NoC is proposed. This router is the 3D extension of MinBD and modifies side-buffer design in MinBD at the same time. Then a deflection routing algorithm based on this router is proposed. The productive output ports of the intra-layer communication packet are calculated according to the direction of destination node and the productive output ports of the inter-layer communication packet are calculated according to the distribution of TSV in current layer. The experimental results show that the network performance of our router is better than reference micro buffered routers’, while even is similar to traditional buffered routers in low and medium network traffic environment.

In view of the difficulties of the current router architecture such as capacity, scalability, and power consumption, a fast-path architecture of IPv6 router suitable for parallel processing is proposed. The fast-path architecture of IPv6 router is designed and implemented using NoC structure. Thereby, a parallel processing structure of IP packets combining the distributed IP address lookup and the parallel IP packet switching is implemented. It is convenient to replace the search algorithm and to expand the hardware scale, and it can improve the overall performance of the router effectively.

With the rapid development of Internet of things, IPv6 has been introduced into wireless sensor networks and widely used in many areas. It is significant to develop routing devices to connect wireless sensor networks and the Internet based on IPv6 technology. In this paper, we present a 6LoWPAN (IPv6 over Low power Wireless Personal Area Networks) border router scheme. The hardware design and software design are discussed and the experimental results demonstrate the feasibility of the router scheme. By using the proposed border router, the network can achieve end-to-end communications between 6LoWPAN nodes and IPv6 hosts in a universal method.

On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and power budgets. While running a traffic trace, however, not all input ports of routers have incoming packets needed to be transferred simultaneously. Therefore, a large number of buffer queues in the network are empty and other queues are mostly busy. This observation motivates us to design router architecture with shared queues (RoShaQ), router architecture that maximizes buffer utilization by allowing the sharing multiple buffer queues among input ports. Sharing queues, in fact, makes using buffers more efficient hence is able to achieve higher throughput when the network load becomes heavy. On the other side, at light traffic load, our router achieves low latency by allowing packets to effectively bypass these shared queues. Experimental results on a 65-nm CMOS standard-cell process show that over synthetic traffics RoShaQ has 17% less latency and 18% higher saturation throughput than a typical virtualchannel (VC) router. Because of its higher performance, RoShaQ consumes 9% less energy per transferred packet than VC router given the same buffer space capacity. Over real multitask applications and E3S embedded benchmarks using near-optimal NMAP mapping algorithm, RoShaQ has 32% lower latency than VC router and targeting the same application throughput with 30% lower energy per packet.

The network-on-chip is becoming an increasingly important component of chip multiprocessors. Recently bufferless deflection routers were proposed, aiming to reduce hardware cost in comparison to classic virtual channel based routers, by eliminating router buffers. We propose RIDER, a low cost deflection router based on an internal rotating ring structure with minimal number of buffers. We compare RIDER with 16 buffers to a wormhole router with 12 buffers, a virtual channel buffered router with 64 buffers, to CHIPPER, a bufferless deflection router with no buffers, and to MinBD, a buffered deflection router with four buffers.

In this paper a router configuration machine for Cisco routers using GUI is presented. It is developed using Visual C# .NET programming, in which the interface provides GUI platforms for various types of configuration for entire series of Cisco routers. It communicates with the Cisco Internetwork Operating System to configure the router. It includes the configuration for all interior routing protocols and all types of most common used tools. The developed system is implemented on different series of Cisco routers and it worked successfully. It is observed that it eliminates the traditional use of command line interface for configuration of Cisco routers. The router configuration machine is such an idea which never existed before in such an easy level. The machine will be a perfect tool for anyone using a router. The machine also allows for real-time monitoring of network devices and constant performance checking. By providing embedded network intelligence at the network device level, the networks can monitor themselves and adapt to changing topologies, without the need of costly external mechanisms. This machine will also be useful for academic purposes and we can use this machine in any Communication Lab.

This paper presents and evaluates router architectures for security networks. Through extensive simulations, the DAMQWR and PD-CB router architecture is shown to best support true fully adaptive routing capability of deadlock recovery schemes while maximizing network performance (102 % higher throughput and 86 % lower network latency than other architectures). Therefore, this router architecture can build a more stable security network by providing a higher network performance.

The non-uniform distributed traffic of chip multi-processor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. At low loads, this router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications' execution time by 16.9% in average compared to low-latency router SWIFT.

High performance computing are useful in performing colossal amount of computation. Interconnect network is crucial when such a tremendous calculation is happening. In order to perform high speed computation, nodes in the system must be connected with a high speed interconnection network. HPC systems have computation and communication parts and performance is limited by communication network rather than computation network. Topology, routing, and flow control are design parameters for interconnect network. Routing algorithm helps the packet to move from source to destination. Router is the key element in implementing adaptive routing algorithm on hardware as it forwards packet from source node to destination through multiple hops. Scheduler and routing controller are responsible for actually forwarding packets based on routing algorithm. The important parameter considered while designing router is a switching technique. There are number of router architecture proposed earlier with switching techniques such as VCT and wormhole. This paper compares previous routers and describes the design of the router used for implementation of the adaptive algorithm on FPGA for 3D Torus. This router uses credit based flow control and Virtual cut through switching technique.

In this Chapter, AIDA-L’s fully-automatic Router is described. The inputs are the floorplan solution generated by the Placer, the netlist and the set of electric-current values for each terminal contained in the netlist. The solution space is then automatically explored, minimizing the total wiring area and complying with a set of electromigration, IR-Drop and wiring symmetry constraints. The Router ensures that each wire does not violate any of the design rules, nor shunts with other wires or shapes of the underneath cells. With all these validations and the huge search space, routing is extremely more complex and computationally more expensive than placement procedures, presented on Chaps. 4 and 5 of this book. This Chapter overviews each of the required tasks implemented in the AIDA-L’s Router, i.e., the planning phases (electromigration-aware wiring topology construction and wiring symmetry detection), the global routing procedures (multiport selection and Steiner point assignment), and, the evolutionary detailed routing phase.

The migration of virtual router has attracted a lot of attention from researchers in the new network architecture field, due to the potential to cope with emerging challenges, such as energy consumption and resource fragmentation problem. In this paper, we focus on general virtual router architecture VRSM (Virtual Router Supporting Migration), composed by a cluster of servers. Compared with other architectures, VRSM introduces intelligently interface plane, management switch and data switch. The interface plane is used to switch data traffic to new forward instances and other two switches can guarantee bandwidth separation between migration traffic and data traffic in migration process. Based on VRSM architecture, we put forward a migration strategy DMVR (Dynamic Migration of Virtual Router), which can dynamically migrate a virtual router instance from one physical server to another without disrupting the network topology. Our experiment shows that DMVR strategy results in minimal impact in the data plane and brief downtime in the control plane.

Router discovery in IPv6 is vulnerable to rogue Router Advertisements (RAs), wherein unintended and possibly incorrect RAs make their way into the network. An IPv6 host obtains several important information from an RA like the default router's address and the prefix for autoconfiguring its IPv6 address. Incorrect data in the RA fields result in operational problems in the network. This can occur as a result of misconfigurations or malicious intentions. A variation of this security threat occurs in the form of a node sending a rogue RA with the spoofed address of the legit router but with the router lifetime field set to zero. This causes the legit router to be removed as the default router for hosts on the subnet. Further, the malicious node could advertise itself as the default router and essentially perform a man-in-the-middle (MITM) attack. This paper demonstrates such a possibility on an IPv6 testbed and presents a possible solution to prevent the same. The implementation of the solution is done on the Linux kernel and results testifying the solution are presented.

In today's Internet scenario, routers play a vital role of connecting two different networks, where in Internet service provider offers services from one network and users can access such services from different networks. For this, routers are customized to fulfill the requirements of such heterogeneous networks. However, customization of router leads to some of the vulnerabilities through which an attacker can compromise the router, and can perform various attacks over the Internet. Extraneous network traffic (unexpected network traffic) is one of the attacks, which can be performed through compromised routers. Here, the main challenge is to differentiate extra data- plane traffic from regular data-plane traffic. In this paper, we propose an analyzer based solution to detect extraneous traffic generated by compromised router. Our analyzer monitors the forwarding behavior of router and detects extraneous packets by comparing source and destination IPs of packets with the consideration of router's performance and efficiency. We analyze the proposed solution by performing different experiments.

Shrinking process technology poses a challenge to network-on-chip design for high performance and energy efficient router architecture to interconnect multiple cores on a chip. Because of its importance, several router micro-architectures are proposed in the literature. In this paper, we propose a novel router architecture, congestion aware switchable cycle adaptive deflection CASCADE router, which dynamically reconfigures itself from single-cycle buffer-less router to two-cycle minimally-buffered router, and vice-versa, based on the router congestion level. The CASCADE router employs congestion aware cycle switching and power-gating to achieve both power and performance efficiency under varying network loads. Experimental results show that, when compared to SLIDER, the state of the art minimally buffered deflection router, the CASCADE router achieves on average 19i¾ź% power reduction and 26i¾ź% flit latency reduction with marginal area overhead.

In view of the family use wireless router in network turning on and the use process common breakdown, this paper systematically analyzes the wireless router causes of network failure, Six methods proposed to solve home wireless network router failure methods and procedures, And wireless network management and maintenance skills of daily, Shows the configuration of the wireless router and network connection troubleshooting typical case, Designed to help users quickly resolve wireless network failure.

This paper presents an innovative router design, called Rotary Router, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or counterclockwise, traveling through every port of the router. These two rings constitute a completely decentralized arbitration scheme that enables a simple, but efficient way to connect every input port to every output port. The proposed router is able to avoid network deadlock, livelock, and starvation without requiring data-path modifications. The organization of the router permits the inclusion of throughput enhancement techniques without significantly penalizing the implementation cost. In particular, the router performs adaptive routing, eliminates HOL blocking, and carries out implicit congestion control using simple arbitration and buffering strategies. Additionally, the proposal is capable of avoiding end-to-end deadlock at coherence protocol level with no physical or virtual resource replication, while guaranteeing in-order packet delivery. This facilitates router management and improves storage utilization. Using a comprehensive evaluation framework that includes full-system simulation and hardware description, the proposal is compared with two representative router counterparts. The results obtained demonstrate the Rotary Router's substantial performance and efficiency advantages.

In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7 x 7 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

Network-on-chip has been proposed to address the global interconnection problems of System-on-Chip. One of the key factors that affects performance of the network-on-chip is its topology. Mesh is the most popular topology because of its scalability and simplicity in physical implementation. But, their performance degrades with size scaling up due to extra hops. Centralized router is proposed as a candidate to overcome the regular topologies drawbacks. This paper discusses the feasibility of a centralized router to replace distributed network-on-chip. A complete evaluation for centralized router and mesh topology is performed over various network-on-chip sizes and different evaluation parameters. Results show that centralized router outperforms in large scale size at the expense of area and power, while in small sizes it outperforms overall evaluation parameters.

With the development of integrated circuit technology, the NoC(Network-on-Chip) has become a research hotspot in recent years. In this paper, we analyze the relevant theories of NoC, especially about the NoC router, as it plays a very important role for connecting the network. We design a low latency NoC router based on the wormhole virtual channel switching, and implement it on RTL (Register Transfer Level). In addition, a two clock-cycles pipelined design pattern is used to improve the efficiency of the router. Finally, we use the “testbench” to test the router's functions with different input signals. The development tool is ISE provided by the company of Xilinx, and combined with Modelsim for waveform simulation.

With increasing number of cores, the communication latency of Network-on-Chip becomes a dominant problem due to complex operations per node. In this paper, we try to reduce communication latency by proposing single-cycle router architecture with wing channel, which forwards the incoming packets to free ports immediately with the inspection of switch allocation results. Also, the incoming packets granted with wing channel can fill in the time-slots of crossbar switch and reduce the contentions with subsequent ones, thereby pushing throughput effectively. We design the proposed router using 65nm CMOS process, and the results show that it supports different routing schemes and outperforms express virtual channel, prediction and Kumar's single-cycle ones in terms of latency and throughput. When compared to the speculative router, it provides 45.7% latency reduction and 14.0% throughput improvement. Moreover, we show that the proposed design incurs a modest area overhead of 8.1% but the power consumption is saved by 7.8% due to less arbitration activities.

In this paper, in order to guarantee more sophisticated QoS for TCP streaming, we expand the function of output buffer control mechanism in QoS-aware IP router. Specifically, we proposed the mechanism which calculates transmission band-width and buffer volume preferentially available according to flow condition only in the QoS-aware router by measuring transmitted packets per flow. Furthermore, through computer simulation, the effectiveness of our proposal is verified.

Multithreaded programming has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors. The performance bottleneck of a multithreaded program is its critical path, whose length is its total execution time. As the number of cores within a processor increases, Network-on-Chip (NoC) has been proposed as a promising approach for inter-core communication. In order to optimize the performance of a multithreaded program running on an NoC based multi-core platform, we design and implement the critical-path driven router, which prioritizes inter-thread communication on the critical path when routing packets. The experimental results show that the critical-path driven router improves the execution time of the test case by 14.8% compared to the ordinary router.

Routers and Forwarders in a Router domain would likely have different amount of hardware Resources. The least capable switch should not hold the performance of the Router network domain to ransom. This write up lists some smart choices the forwarders and routers in the Router domain can make to most efficiently utilize the hardware forwarding capabilities of each node in the network. In a Router domain, all forwarders and routers belonging to a single Router domain keep every other Forwarder or router updated of all the host routes for each host known and present in the network. The above is done for every subnet in the Router domain. Each forwarder and router installs all the routes in the fast path forwarding database (for example hardware forwarding tables). In this new scheme, all the routers and forwarders learn all the routes, build the topology table for all subnets, but the difference is the router/forwarder can choose to put subnet of the routes in the fast path database (hardware database). This would save of the hardware resources, without sacrificing the network performance in most cases. In the cases where network path chosen is potentially suboptimal a further set of enhancements comes and loosens the optimization to further improve the network performance without wasting the forwarding resource utilization.