156 results on '"Breuil, L."'
Search Results
2. Interaction médicamenteuse médiée par la P-glycoprotéine au niveau de la barrière hémato-encéphalique : comparaison in vitro et in vivo par imagerie TEP de la dompéridone et du métoclopramide
3. Neuroimagerie pharmacologique utilisant l’imagerie TEP au 18F-FDG pour évaluer la réponse du système nerveux central en présence de buprénorphine chez le rat
4. Assessment of tunnel oxide and poly-Si channel traps in 3D SONOS memory before and after P/E cycling
5. A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash
6. High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction
7. [18F]2-fluoro-2-désoxy-sorbitol pour le suivi quantitatif de la perméabilité accrue de la barrière hémato-encéphalique induite par les ultrasons focalisés
8. [11C]VU0071063 : un nouveau radiotraceur marqué au carbone-11 pour l’imagerie TEP cérébrale des récepteurs à la sulfonylurée de type 1 (SUR-1)
9. Understanding the kinetics of Metal Induced Lateral Crystallization process to enhance the poly-Si channel quality and current conduction in 3-D NAND memory
10. Rare-earth aluminates as a charge trapping materials for NAND flash memories: Integration and electrical evaluation
11. Optimization of gate stack parameters towards 3D-SONOS application
12. Effect of high temperature annealing on tunnel oxide properties in TANOS devices
13. Impact of Charge Trapping and Depolarization on Data Retention Using Simultaneous P–V and I–V in HfO₂-Based Ferroelectric FET
14. High-k dielectrics for hybrid floating gate memory applications
15. First demonstration of ferroelectric Si:HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application
16. Understanding the memory window in 1T-FeFET memories: a depolarization field perspective
17. Lateral Distribution of Electrons Trapped in Nitride Layers
18. Defect profiling in FEFET Si:HfO2 layers
19. Integration of Ruthenium-based Wordline in a 3-D NAND Memory Devices
20. Kinetic models to improve the interpretation of the hepatic transport of 99mTc-mebrofenin
21. Refining the use of PET imaging to detect moderate changes in P-gp function at the blood-brain barrier
22. Scaling effects in dual-bit split-gate nitride memory devices
23. Impact of SiON tunnel layer composition on 3D NAND cell performance
24. Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices
25. First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices
26. Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND
27. In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices
28. Impact of discrete trapping in high pressure deuterium annealed and doped poly-Si channel 3D NAND macaroni
29. Liberalization of water services in europe: the end of the french water exception?
30. First-principles study of oxygen and aluminum defects in beta-Si3N4: Compensation and charge trapping
31. Intrinsic electron traps in atomic-layer deposited HfO2 insulators
32. Improvement of Poly-Si Channel Vertical Charge Trapping NAND Devices Characteristics by High Pressure D2/H2 Annealing
33. Electron energy distribution in Si/TiN and Si/Ru hybrid floating gates with hafnium oxide based insulators for charge trapping memory devices
34. Les services publics d'eau et d'assainissement : vers la fin d'une exception française?
35. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory
36. Advantages of the FinFET architecture in SONOS and Nanocrystal memory devices
37. Quels modèles de gouvernance pour l'amélioration de la desserte en eau des grandes villes dans les pays en développement ? Rôle de la participation des usagers au sein de partenariats innovants
38. Rethink PPP in water for developing countries: how to combine contractual, institutional and participatory approaches
39. Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations
40. Defects characterization of Hybrid Floating Gate/Inter-Gate Dielectric interface in Flash memory
41. Stacked-etch induced charge loss in Hybrid Floating Gate cells using high-κ Inter-Gate Dielectric
42. Integration of a multi-layer Inter-Gate Dielectric with hybrid floating gate towards 10nm planar NAND flash
43. (Invited) High-k Dielectrics and High Work Function Metals for Hybrid Floating Gate NAND Flash Applications
44. A novel multilayer Inter-Gate Dielectric enabling up to 18V Program / Erase window for planar NAND flash
45. Instability study of high-κ Inter-Gate Dielectric stacks on hybrid floating gate flash memory
46. Intrinsic electron traps in atomic-layer deposited HfO2 insulators.
47. Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology
48. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology
49. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory
50. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.