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Though exponential distributions are ubiquitous in statistical physics and related computational models, directly sampling them from device behavior is rarely done. The superparamagnetic tunnel junction (SMTJ), a key device in probabilistic computing, is known to naturally exhibit exponentially distributed temporal switching dynamics. To sample an exponential distribution with an SMTJ, we need to measure it in the time domain, which is challenging with traditional techniques that focus on sampling the instantaneous state of the device. In this work, we leverage a temporal encoding scheme, where information is encoded in the time at which the device switches between its resistance states. We then develop a circuit element known as a probabilistic delay cell that applies an electrical current step to an SMTJ and a temporal measurement circuit that measures the timing of the first switching event. Repeated experiments confirm that these times are exponentially distributed. Temporal processing methods then allow us to digitally compute with these exponentially distributed probabilistic delay cells. We describe how to use these circuits in a Metropolis-Hastings stepper and in a weighted random sampler, both of which are computationally intensive applications that benefit from the efficient generation of exponentially distributed random numbers.

Artificial neural networks have advanced due to scaling dimensions, but conventional computing faces inefficiency due to the von Neumann bottleneck. In-memory computation architectures, like memristors, offer promise but face challenges due to hardware non-idealities. This work proposes and experimentally demonstrates layer ensemble averaging, a technique to map pre-trained neural network solutions from software to defective hardware crossbars of emerging memory devices and reliably attain near-software performance on inference. The approach is investigated using a custom 20,000-device hardware prototyping platform on a continual learning problem where a network must learn new tasks without catastrophically forgetting previously learned information. Results demonstrate that by trading off the number of devices required for layer mapping, layer ensemble averaging can reliably boost defective memristive network performance up to the software baseline. For the investigated problem, the average multi-task classification accuracy improves from 61 % to 72 % (< 1 % of software baseline) using the proposed approach.

Superparamagnetic tunnel junctions (SMTJs) are promising sources of randomness for compact and energy efficient implementations of probabilistic computing techniques. Augmenting an SMTJ with electronic circuits, to convert the random telegraph fluctuations of its resistance state to stochastic digital signals, gives a basic building block known as a probabilistic bit or $p$-bit. Though scalable probabilistic computing methods connecting $p$-bits have been proposed, practical implementations are limited by either minimal tunability or energy inefficient microprocessors-in-the-loop. In this work, we experimentally demonstrate the functionality of a scalable analog unit cell, namely a pair of $p$-bits with programmable electrical coupling. This tunable coupling is implemented with operational amplifier circuits that have a time constant of approximately 1us, which is faster than the mean dwell times of the SMTJs over most of the operating range. Programmability enables flexibility, allowing both positive and negative couplings, as well as coupling devices with widely varying device properties. These tunable coupling circuits can achieve the whole range of correlations from $-1$ to $1$, for both devices with similar timescales, and devices whose time scales vary by an order of magnitude. This range of correlation allows such circuits to be used for scalable implementations of simulated annealing with probabilistic computing.

The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann bottleneck by performing computation in or near memory. An inevitability of transferring neural networks onto hardware is that non-idealities such as device-to-device variations or poor device yield impact performance. Methods such as hardware-aware training, where substrate non-idealities are incorporated during network training, are one way to recover performance at the cost of solution generality. In this work, we demonstrate inference on hardware neural networks consisting of 20,000 magnetic tunnel junction arrays integrated on a complementary metal-oxide-semiconductor chips that closely resembles market-ready spin transfer-torque magnetoresistive random access memory technology. Using 36 dies, each containing a crossbar array with its own non-idealities, we show that even a small number of defects in physically mapped networks significantly degrades the performance of networks trained without defects and show that, at the cost of generality, hardware-aware training accounting for specific defects on each die can recover to comparable performance with ideal networks. We then demonstrate a robust training method that extends hardware-aware training to statistics-aware training, producing network weights that perform well on most defective dies regardless of their specific defect locations. When evaluated on the 36 physical dies, statistics-aware trained solutions can achieve a mean misclassification error on the MNIST dataset that differs from the software-baseline by only 2 %. This statistics-aware training method could be generalized to networks with many layers that are mapped to hardware suited for industry-ready applications., Comment: 17 pages, 9 figures

One of the big challenges of current electronics is the design and implementation of hardware neural networks that perform fast and energy-efficient machine learning. Spintronics is a promising catalyst for this field with the capabilities of nanosecond operation and compatibility with existing microelectronics. Considering large-scale, viable neuromorphic systems however, variability of device properties is a serious concern. In this paper, we show an autonomously operating circuit that performs hardware-aware machine learning utilizing probabilistic neurons built with stochastic magnetic tunnel junctions. We show that $in \ situ$ learning of weights and biases in a Boltzmann machine can counter device-to-device variations and learn the probability distribution of meaningful operations such as a full adder. This scalable autonomously operating learning circuit using spintronics-based neurons could be especially of interest for standalone artificial-intelligence devices capable of fast and efficient learning at the edge.

Naturally random devices that exploit ambient thermal noise have recently attracted attention as hardware primitives for accelerating probabilistic computing applications. One such approach is to use a low barrier nanomagnet as the free layer of a magnetic tunnel junction (MTJ) whose magnetic fluctuations are converted to resistance fluctuations in the presence of a stable fixed layer. Here, we propose and theoretically analyze a magnetic tunnel junction with no fixed layers but two free layers that are circularly shaped disk magnets. We use an experimentally benchmarked model that accounts for finite temperature magnetization dynamics, bias-dependent charge and spin-polarized currents as well as the dipolar coupling between the free layers. We obtain analytical results for statistical averages of fluctuations that are in good agreement with the numerical model. We find that the free layers with low diameters fluctuate to randomize the resistance of the MTJ in an approximately bias-independent manner. We show how such MTJs can be used to build a binary stochastic neuron (or a p-bit) in hardware. Unlike earlier stochastic MTJs that need to operate at a specific bias point to produce random fluctuations, the proposed design can be random for a wide range of bias values, independent of spin-transfer-torque pinning. Moreover, in the absence of a carefully optimized stabled fixed layer, the symmetric double-free layer stack can be manufactured using present day Magnetoresistive Random Access Memory (MRAM) technology by minimal changes to the fabrication process. Such devices can be used as hardware accelerators in energy-efficient computing schemes that require a large throughput of tunably random bits.