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Light-to-digital converters (LDCs) are essential components in photoplethysmography (PPG) readout chains. Over the past decade, PPG sensors have gathered increased interest due to their non-invasiveness and employment in a wide variety of applications. Among these are cardiovascular monitoring, brain mapping, glucose sensing, skin cancer detection, ozone pollutant sensing, and commercial fitness tracking devices. This article offers a review of recent developments in PPG monitoring, with a specific focus on LDCs. The critical challenges, such as light-emitting diode (LED) power consumption, low perfusion index (PI), ambient light interference, and motion artifacts (MAs), are discussed in detail. Different sampling methods (uniform aggressive, compressive, and event-driven) are analyzed to provide an overview of the mitigation techniques of the LED power consumption issue. Moreover, specific circuit solutions to overcome the remaining challenges are explored within the power consumption and signal quality trade space. Recent advances in LDCs employing on-chip photodetectors (PDs) and dc cancellation circuits are discussed as they significantly improve the noise performance of the readout and provide a considerable overall power reduction. The article also evaluates state-of-the-art (SoA) circuit design techniques, providing essential considerations and intuitions. Lastly, it outlines future development trends and insights, charting a course for continued innovation in this rapidly evolving field.

To guarantee the required performance and proper stability, a dc–dc regulator needs to be equipped with a tailored compensation network. A proportional-integral-derivative (PID) controller is typically employed and the required compensator transfer function is obtained from the study of the dc–dc converter frequency responses. Focusing on the widely adopted analog compensator, such required transfer function can be implemented mostly following two approaches. An implementation is based on an open-loop-amplifier (OLA), equipped with input and output filter networks, while another solution deploys a closed-loop-amplifier (CLA), locally closed in feedback by means of a filter network. This article presents a fair comparison between the two most common architectures of analog compensators for switched-inductor dc–dc converters. In the analyses, the trade-offs are detailed, starting from area, mismatch, system considerations, complexity, and limits, with the goal to empower the designer with a comprehensive breakdown. Although not providing disruptive innovations but retaining a tutorial flavor, this article aims to be a unified approach to the design of analog compensators for dc–dc converters.

This brief presents a fast transient LDO with high power supply rejection ratio (PSRR) over 100-kHz based on adaptive biasing, dynamic biasing technique and a current mode feed-forward amplifier (CMFFA). The dynamic biasing improves the load transient response and the adaptive biasing benefits the loop stability. The CMFFA introduces a left-half-plane zero to compensate for the non-dominant pole without large current consumption. Moreover, a impedance adaptive circuit is also used in this design: it ensures the DC gain and pushes a non-dominant pole to high frequency. Through these methods, the proposed LDO is stable over full load range, from 0mA to 150mA, it achieves fast transient response and high PSRR with a low quiescent current. The LDO is fabricated in a 0.6- $\mu $ m CMOS technology. The output voltage can be regulated from 1.8V to 3.3V and the load capacitance is 1 $\mu $ F. For a 150mA load step and a 3.3V output voltage, the maximum undershoot voltage is 38.6mV. At maximum load condition, a 41dB PSRR is achieved at 100-kHz and the loop gain bandwidth product is 1.9MHz. The DC gain is around 70dB over the full load range. The measured load regulation and line regulation are 0.06mV/mA and 1mV/V, respectively. The LDO has a minimum quiescent current of 9.6 $\mu $ A without load. Finally, the proposed LDO achieves a FOM1 of 16.47ps and a FOM2 of 123.52 $\mu $ V.

This article presents a bipolar junction transistor (BJT)-based smart temperature sensor employing a noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC). This approach, never explored before within a temperature sensing system, was chosen to exploit the low energy/conversion benefit peculiar to SAR-based solutions while overcoming their quantization-dominated resolution with an error-feedback technique. In addition, the system features a complete current-mode architecture enabling op-amp less signal processing and resulting in a highly compact design. Developed and fabricated in a standard 180-nm CMOS process, the sensor exhibits an active area of $\mathrm {0.057~\text{mm}^2}$ and draws a 34- $\mu \text{A}$ total current from a 1.8-V supply. Experimental results in the $\mathrm {-50~ \text {C}}$ to $\mathrm {110~ \text {C}}$ sensing range demonstrate a 92-mK resolution in a conversion time of $\mathrm {80~ {\mu } \text { s}}$ .