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Over the last 20 years, the field of Smart Dust has been proposed and demonstrated. Almost in the same period, implantable and wearable sensors for human monitoring have been actually successfully introduced in the market. The present research about Smart Dust is actually in the field of Dust for brain applications (Neural Dust) or for metabolism monitoring (Body Dust). Aim of this feature article is to review all the developments presented so far in literature, and then define the next steps and challenges. First, we see the field of Smart Dust and, then, its application to human sensing. The paper starts from details about the early phases of the research in the area, and first developments. Then, it reviews the recent advancements in the field, for then closing with the definition of the still-open challenges for realizing motes that could spread in human body as thousands of individual sensors in a kind of sensing active network capable to provide telemetry from inside the body. The Body Dust concept discussed in this article is well beyond the present concepts of wearable or implantable devices. These last are actually entering into the market to provide personalized and more precise medicine to human health, while the Body Dust concept definitely represents the future of humans monitoring, still opens to scientific explorations.

In this work, we study the effect of transistor downscaling in a wireless communication circuit for Body Dust application. The system requires a chip lateral size smaller than 10 mu m miming the typical size of a red blood cell and so, supporting free circulation in human tissues. Moreover, an ultra-low-power architecture is needed since the system is battery-less and wirelessly powered via acoustic power transfer. The aim of this paper is to present a data communication system for Body Dust systems, which works from the multiplexed sensor read-out front-end to the transmitter back-end taking account diagnostic information on different metabolite concentrations in human body. This work shows that scaling the architecture from a 0.18-mu m to 28-nm CMOS processes, it is possible to improve both size and power consumption. The improvement is about 40 times in size (2000 mu m(2) down to 50 mu m2) and two order of magnitude in average power consumption (10 mu W to cents of nW).