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session 2B: Process Integration; International audience; In this paper, the Bias Temperature Instability effects of Lanthanum (La) and Aluminum (Al) incorporation, used for threshold voltage adjustment by dipole formation at the SiO2/HfON interface into the FDSOI gate dielectrics has been studied. When compared at the same oxide electric field (Eox), incorporation of La causes significant enhancement of intrinsic NBTI (Negative Bias Temperature Instability) effect and it reduces the already low PBTI (Positive Bias Temperature Instability) effect. On the other hand, comparison at the same Gate voltage (Vg) does not show the same behavior possibly due to the reduction of oxide field (Eox) by La dipole effect. Incorporation of Al does not have a significant impact on NBTI but it causes significant enhancement of PBTI, when compared both at the same Eox or same Vg. NBTI/PBTI degradations well correlate to the La and Al effective doses in the gate dielectrics.

State of the art CMOS gate stacks as well as devices are more and more complex with many possible technological options. This paper addresses the measurement and the understanding of several dipoles which may be present in the FDSOI gate stack (generation 28-14-10 nm). These dipoles are namely the intrinsic SiO2/high-k dipole, the dipoles induced by Lanthanum and Aluminum doping to change the effective workfunction, and the Germanium induced dipole in the case of SiGe channel. Some reliability studies (NBTI) will be presented on these stacks, leading to an interesting regard on physical mechanisms. The paper first review the objectives and the effects of Aluminum and Lanthanum doping in the gate stack. Aluminum and Lanthanum are used for effective workfunction engineering, shifting the effective workfunction respectively towards P+ and towards N+. This shift has been shown to be due not to charges created inside the stack but instead to the modification of the built in dipole at the bottom oxide-high k (here HfO2) interface. Globally speaking, the observed shift is around 30 to 60 meV per 10E14 at/cm2 of introduced species in the stack, only a part of them being active in the dipole formation [1]. Theoretical investigations through ab-initio simulations will be presented to explain this phenomena. Using this technology, a shift of several hundred millivolts can be obtained to adjust Vt for NMOS and PMOS in an industrial way. Notice that depending on the architecture and the sequential order of doping of NMOS and PMOS, both type of dopants may be present in each kind of device, NMOS and PMOS. Due to this observation, the effect of both Aluminum and Lanthanum is considered studied in this paper for NMOS and PMOS. Previous study on Bulk CMOS on SiGe concluded to the presence of a dipole at the interface SiO2/SiGe [2]. This dipole was shown to shift by around 150 mV the SiGe the band structure respectively to an ideal case without dipole. In the case of FDSOI with SiGe, SiGe exibits one interface with the high-k bottom SiO2 oxide and one interface with the SiO2 Buried oxide (BOX). Experiments made on PMOS FDSOI with SiGe channel actually evidence the two opposite dipoles at the interface SiO2bottom/SiGe and at the interface SiGe/Box [3]. This understanding must significantly improve the whole modeling of the structure. The bias temperature instabilities effects (NBTI and PBTI) induced by Lanthanum and Aluminum incorporation are then briefly discussed. An interesting theoretical case is the NBTI with La doping. When compared at same electric field, which is the usual way in literature to analyze physically the data, incorporation of La causes significant degradation of intrinsic NBTI. On the other hand comparison at the same gate voltage does not show at all the same results. The results of this work tend to evidence a physical law exhibiting a gate voltage dependence instead of an electric field dependence. This is supported by a large matrix of experiments (VGi, [La]i) [4]. The pro and contrary arguments for the two points of view will be discussed in the full paper as well as their implications on the device lifetime. References: [1] C. Suarez-Segovia, Electron Device Letters, p.379, 2017. [2] A. Soussou et al., Micro. Eng., 109, p.282, 2013. [3] B. Mohamad et al., INFOS 2017. [4] P. Kumar et al., IRPS 2017