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This paper describes a chopper stabilized amplifier, obtained using an input chopper for modulation, an AC coupling for offset rejection and a correlated double sampling structure for demodulation, avoiding ripple spurs. The operational amplifier has a rail-to-rail input stage, with a supply voltage range from 1.8V to 5V. It is characterized by a multipath nested Miller compensation network with double pole-zero cancellation. The circuit achieves a simulated 130dB-dc-gain with a current consumption of 20 mu A, suitable for low-power application. Equivalent input offset has been evaluated by Montecarlo simulations demonstrating a maximum standard deviation of about 4 mu V

In this paper a dedicated integrated front-end for the Triple-GEM (Gas Electron Multiplier) detector is presented. The design has been realized in 0.13 mu m CMOS technology. This system aims to improve performance with respect to the state-of-the-art on these types of detectors, regarding adaptability, portability, power consumption and on-chip data processing. The front-end is composed by 8-input-channels. Each channel performs the charge-vs-time conversion, and then the signal is definitively converted into digital domain. For this aim a Charge-Sensitive Preamplifier (CSP), and a Charge-to-Time Converter (CTC) are implemented. An automatic on-chip calibration circuit is also included, in order to compensate CMOS technological process/temperature variations. The system is able to manage a 15 pF detector capacitance. The maximum count rate is 4.10(6) counts-per-second (cps) and the power consumption is 3.8 mW/ch. The Equivalent Noise Charge (ENC) is 418 e(-). The front-end compares favorably with the state-of-the-art

In vista dell'edizione della cosiddetta IV parte della 'Cronaca di Partenope', in preparazione per l'ISIME, si fornisce uno specimen di edizione del capitolo che narra l'ingresso a Napoli di Carlo di Durazzo.

Rilettura storico-linguistica delle formule testimoniali in volgare dei placiti di Capua (marzo 960) e Sessa Aurunca (963) a partire dai testi dei documenti giuridici in cui sono inserite

The design of an automatic biasing system for High-Electron-Mobility-Transistors is here presented (HEMT-Biasing-System, HBS). The HBS automatically regulates the operating point of an off-chip multistage HEMT block. A proper automatic algorithm is implemented in order to maximize the HEMT transconductance (gm) efficiency (defined as gm/IDS ratio). This is an important feature in several HEMT-based systems, since they are used in LNA stages, where noise/power trade-off is a key aspect. Interfacing CMOS and HEMT technologies features several design issues, like negative gate-source voltage (to be managed by a CMOS circuits for HEMT switch-off operation) and closed-loop stability (due to the presence of very large off-chip capacitance - 100nF). The System here presented manages all these issues with tailored circuit solutions. A prototype has been designed in CMOS 0.35μm technology. It consumes 6.2mW (excluding the current consumption for HEMT driving).

In this paper a 5th order low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz -3dB-bandwidth is obtained by a prototype of the filter simulated in 45nm CMOS technology node (also Process-Voltage-Temperature simulations are available). The overall power consumption is 9mW from a single 1.2V supply voltage. 54dB@THD>40dBc is the SNR at 0dB gain.

In this work a new concept of hybrid lamps burner is presented. The High Intensity Discharge (HID) lamps and the new generation Light Emitting Diodes (LED) lamps can be driven by the same electronic ballast using this hybrid ASIC in 0.35m CMOS technology. In the state-of-art the electronic ballasts are managed by powerful general-purpose devices (usually FPGA or microcontroller). These devices are not customized for the specific application. Thus they have a larger area occupation and power consumption compared to ASIC solution. The designed ASIC power consumption is 35 mW and the package area is about 6.5 cm2 against 550 mW and 6.5 cm2 for commonly used PIC 18FXX2. © 2011 IEEE.

In this paper the design of a 3rd-order 16 bit 20 kHz-bandwidth discrete-time σδ modulator with voltage- controlled oscillator (VCO)-based quantizer is presented. This design is motivated by the trends towards die size and power consumption reduction together with performance robustness. In this direction, the flash converter embedded in a multi-bit σδM is here replaced by a VCO and digital counter, resulting in a compact fully-digital quantizer implementation. This solution would greatly exploit the technology scaling. Moreover in the proposed feed-forward architecture all feed-forward paths are summed within the last integrator of the σδ loop filter, thereby eliminating the need for an analog summation amplifier at the quantizer input The presented 3rd-order σδM features 110 dB-SNR, 104 dB-SNDR (i.e. 16 bit-ENOB). © Springer Science+Business Media, LLC 2011.

In this paper an approach for the design of low-voltage analog Active-RC filers is presented. This technique is based on the use of different common mode levels at the opamp inputs and the filter inputs and outputs. A design example of a 600mV supply voltage 4th order low-pass analog filter for UMTS receivers is reported. The filter is designed in a 0.13μm CMOS technology with a 600mV supply voltage. The filter features a wide swing performance (THD=40dB@800mVpp,differential output signal amplitude), and high dynamic range (47 dB). © 2006 IEEE.