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The single flux quantum (SFQ) digital superconducting logic family has been proposed for the scalable control of next-generation superconducting qubit arrays. In the initial implementation, SFQ-based gate fidelity was limited by quasiparticle (QP) poisoning induced by the dissipative on-chip SFQ driver circuit. In this work, we introduce a multi-chip module architecture to suppress phonon-mediated QP poisoning. Here, the SFQ elements and qubits are fabricated on separate chips that are joined with In bump bonds. We use interleaved randomized benchmarking to characterize the fidelity of SFQ-based gates, and we demonstrate an error per Clifford gate of 1.2(1)%, an order-of-magnitude reduction over the gate error achieved in the initial realization of SFQ-based qubit control. We use purity benchmarking to quantify the contribution of incoherent error at 0.96(2)%; we attribute this error to photon-mediated QP poisoning mediated by the resonant mm-wave antenna modes of the qubit and SFQ-qubit coupler. We anticipate that a straightforward redesign of the SFQ driver circuit to limit the bandwidth of the SFQ pulses will eliminate this source of infidelity, allowing SFQ-based gates with fidelity approaching theoretical limits, namely 99.9% for resonant sequences and 99.99% for more complex pulse sequences involving variable pulse-to-pulse separation., Comment: 15 pages, 8+4 figures, 1 table

Superconducting optoelectronic hardware is being explored as a path towards artificial spiking neural networks with unprecedented scales of complexity and computational ability. Such hardware combines integrated-photonic components for few-photon, light-speed communication with superconducting circuits for fast, energy-efficient computation. Monolithic integration of superconducting and photonic devices is necessary for the scaling of this technology. In the present work, superconducting-nanowire single-photon detectors are monolithically integrated with Josephson junctions for the first time, enabling the realization of superconducting optoelectronic synapses. We present circuits that perform analog weighting and temporal leaky integration of single-photon presynaptic signals. Synaptic weighting is implemented in the electronic domain so that binary, single-photon communication can be maintained. Records of recent synaptic activity are locally stored as current in superconducting loops. Dendritic and neuronal nonlinearities are implemented with a second stage of Josephson circuitry. The hardware presents great design flexibility, with demonstrated synaptic time constants spanning four orders of magnitude (hundreds of nanoseconds to milliseconds). The synapses are responsive to presynaptic spike rates exceeding 10 MHz and consume approximately 33 aJ of dynamic power per synapse event before accounting for cooling. In addition to neuromorphic hardware, these circuits introduce new avenues towards realizing large-scale single-photon-detector arrays for diverse imaging, sensing, and quantum communication applications., Comment: 23 pages, 20 figures