35 results on '"Bertulessi, Luca"'
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2. Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications
3. A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity
4. A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS
5. A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization
6. 4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
7. A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC With Charge Linearization
8. A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
9. A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
10. A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
11. A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters
12. A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
13. Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs
14. Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
15. A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
16. A $68.6\text{fs}_{\text{rms}}$-Total-integrated-Jitter and $1.5\mu \mathrm{s}-\text{LocKing}$-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
17. A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
18. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-$N$ Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
19. A Digital PLL With Multitap LMS-Based Bandwidth Control
20. A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
21. Digital PLLs: the modern timing reference for radar and communication systems
22. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
23. 32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
24. 32.3 A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
25. 17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
26. 17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
27. A 250-Mb/s Direct Phase Modulator With −42.4-dB EVM Based on a 14-GHz Digital PLL
28. A 30-GHz Digital Sub-Sampling Fractional-$N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
29. 16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
30. A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking.
31. A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation
32. A Background Calibration Technique to Control the Bandwidth of Digital PLLs
33. A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
34. A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
35. Analysis of power efficiency in high-performance class-B oscillators
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