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In this letter we present a fast triple voltage quenching circuit (TVQC) with an integrated $40~\mu \text{m}$ diameter single-photon avalanche diode (SPAD) in 0.35- $\mu \text{m}$ CMOS. By pre-biasing the switching MOSFETs the reaction time of the TVQC is kept small, leading to a total quenching time of only 1.4 ns of which 0.61 ns are actively quenched. This short reaction time reduces the avalanche charge and therefore also the afterpulsing probability (APP). The dead time is adjustable from 7.9 ns to 200 ns, which allows further reducing the APP. Experimental verification shows an APP of 2.1% at a dead time of 30 ns. Using an integrated SPAD with a thick absorption zone allows achieving a photon detection probability (PDP) of 28.8% at 850 nm, while showing a peak PDP of 53.1% at 657 nm, both at 9.9 V excess bias.

An optical sensor IC in 0.35- $\mu \text{m}$ CMOS is presented containing a single-photon avalanche diode (SPAD) and a fast quadruple-voltage quenching circuit (QVQC). The QVQC features a fast active quenching time of 0.93 ns, a total quenching time of 1.9 ns, and an adjustable total dead time (8.6–200 ns) to reduce the afterpulsing probability (APP). To verify the quenching performance, the circuit was integrated with a 40- $\mu \text{m}$ diameter SPAD. Experiments show the reduction of afterpulsing by a low detection threshold and by fast quenching with a slew rate of 13.8 GV/s. Thus, an APP of 3.2% at 27-ns dead time, a peak photon detection probability (PDP) of 67.6% at 652 nm, and a PDP of 34.7% at 854 nm were measured at 13.2-V excess bias.

An ultralow-power and low-complexity impulse radio ultrawideband (IR-UWB) transmitter (TX) is fabricated in the low-cost 180-nm United Microelectronics Corporation (UMC) CMOS technology. The TX offers control of the power spectral density (PSD) by using a tunable pulse generator and a controllable switched oscillator. It supports on-off keying (OOK) coding and occupies a total die area of 0.35 mm2. The measured results show the transmitter output amplitude of 130 mVp-p with the pulse width of 1.0 ns, and the PSD with 10-dB bandwidth from 3 to 8.8 GHz. The total dc power consumption is 0.6 mW, corresponding to the energy consumption of 3 pJ/pulse at 200-MHz pulse repetition frequency.

Experimental demonstration of a quantum random number generator based on one single-photon avalanche diode (SPAD) detector, a T / ( T − t ) pulse-shaped laser, and an field-programmable gate array (FPGA) acquisition module is presented. An integrated laser driver drives an external laser diode at 670 nm wavelength, whereas the SPAD with a photon detection probability of 18.5% is integrated together with an active quenching-resetting circuit. The SPAD detector generates counts for the interarrival time (IAT) measurement system implemented in an FPGA, where the change of the IATs between consecutive pulses is used to derive a random bit stream. It is shown how the application of a pulse-shaped laser driver can increase the performance of the system as compared to the continuous-wave operation of the laser diode to achieve the maximum generation rate of 5 Mbps while using a single SPAD. The generated numbers pass all randomness tests of the National Institute of Standards and Technology (NIST), Dieharder, and ENT test (pseudorandom number sequence test) suits.

A 38.5 Gb/s optical receiver has been fabricated in a 130 nm SiGe-BiCMOS technology for being employed in a Radio over Fiber transceiver for 5G remote radio head application. As a transimpedance topology, a common base amplifier is used to provide a low resistance input impedance to relax connecting a photodiode with relatively high capacitance. The transimpedance amplifier (TIA) is followed by the capacitive degeneration limiting amplifier to create a degree of freedom and relax the trade-off between the gain-bandwidth product and the linearity of the receiver. Analytical methods have been investigated to provide a low-noise and high gain design. Calibrated S-parameter measurement has been done which represents a 27-GHz 3-dB bandwidth with a differential gain of 49 dB$\Omega$ with a total power consumption of 160 mW for the entire receiver. The optical receiver has also been tested in the time domain by using a 35-GHz photodetector with a responsivity of 0.1 A/W and a capacitance of 90 fF. Eye diagram measurements have revealed that the optical receiver can provide a BER of $6.37\times 10^{-6},1.3\times 10^{-4}$, and $1.7\times 10^{-3}$ for a data rate of15, 25, and 35 Gb/s at an input current of 32$\mu$A respectively. The fabricated receiver occupies an area of 930 $\mu m\times 930\mu m$ including bond pads.

A voltage-controlled current amplifier/attenuator in a standard 0.35- ${\mu }\text{m}$ CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm2. A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 ${\mu }\text{W}$ with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator.

An integrated quadruple voltage mixed quenching, and active resetting circuit (Q2RC) in a 150 nm CMOS process is presented in this paper. The Q2RC features an excess-bias voltage of 7.2 V, which is four times the 1.8 V supply voltage. The dead time can be adjusted from 7 ns to 29 ns, which corresponds to the count rate range from 34 Mcps to 142 Mcps. Post-layout simulation results for an external SPAD with an equivalent parasitic capacitance of 4 pF are reported. The achieved quenching time of the Q2RC is 1.75 ns, which results in 4.05 GV/s quenching slew rate, while the delay time is 1.1 ns, and the resetting time is 2.55 ns.

A voltage-controlled current source in 0.35 μm BiCMOS technology is presented. A linear relationship between the control voltage and the output current is achieved by using first generation current conveyors in configuration of simple voltage-to-current converters. The control voltages of the DC and the AC output currents are completely independent of each other. The current source is intended for the generation of small currents in a sub-microampere range and in a frequency range of a few hundreds of megahertz. The measured and simulated results confirm that the smallest amplitudes of the generated currents are down to 100 nA, with a single supply voltage of 1.3 V. The small-signal bandwidth ranges from 15 up to 900 MHz.

An electronic integrated circuit (EIC) and a silicon photonic integrated circuit (PIC) are 3D-integrated. The EIC using the complementary metal–oxide–semiconductor (CMOS) part of STMicroelectronics’ BCD8sp $0.16~\mu \text{m}$ technology controls all 768 switches in the PIC individually and monitors them with 84 transimpedance amplifiers. A scalable analog–digital approach with a cell size of $100\times 100\,\,\mu \text {m}^{2}$ for thermal control of optical ring resonator switch matrices is introduced. An electrical power consumption of 220 mW for all electronic control circuits of the optical switch matrix is resulting in 5.5% of the power needed by a constant-voltage control approach.

We present experimental results obtained from full-waveform measurements of single-event transients (SETs) occurring in the conventional two-input AND and OR gates under focused heavy-ion radiation. Chips with test circuits were fabricated in a 65-nm bulk CMOS technology, and were irradiated in a microbeam facility using 197Au and 48Ca species. The resulting SETs were sensed using a dedicated on-chip analog multiplexer circuit. The obtained position-dependent ion hit responses were analyzed, and the strong evidence of charge-sharing-induced pulse quenching was observed. For SETs that propagated through the inverting stage of AND and OR circuits, a significant degradation of measured SET pulse widths and heights was seen. These observations are in good accordance with earlier published simulation and experimental results based on inverter chains. Test circuits also exhibited distinct SET responses depending on their logic state, making the AND gate a better candidate for exploiting the pulse quenching effect when circuits are placed in a triple well.

A fully integrated 0.35- $\boldsymbol {\mu }\text{m}$ CMOS optical data receiver with a 50- $\boldsymbol {\mu }\text{m}$ diameter single-photon avalanche-diode and a cascoded gating circuit enabling a maximum excess bias voltage of 6.6 V (to obtain a high photon detection efficiency) is presented. To optimize the sensitivity in presence of dark counts and after-pulsing a decision threshold of 2–5 photon counts can be selected. For red light (635 nm) and nonreturn-to-zero modulation the sensitivity is −64 dBm for 20 Mb/s with 100 MHz clock frequency and −57 dBm for 50 Mb/s with 250 MHz.

A laser diode current driver with $(1-t/T)^{-1}$ time dependence in 0.35- $\mu\text{m}$ BiCMOS technology is presented in this brief. It is intended for application in optical quantum random number generators. The current driver is based on the balanced type of a bipolar junction transistor translinear loop with a sawtooth current as one of its inputs. The controllability of the frequency, shape, amplitude, and dc level of the current pulses is provided. The achievable frequency bandwidth of the current pulses is up to 100 MHz. A relative error of the measured waveform at a frequency of 25 MHz is smaller than 3% in 97.4% of the time period of interest.

This letter presents a monolithically integrated latch-type synchronous optical receiver, consisting of a regenerative latch with two highly effective, low-capacitance pin photodiodes connected to it (one of them blocked to the light). Two adjustable reference currents are used to compensate the dynamic offset created by the asymmetries in the parasitic capacitance of the photodiodes. This dynamic offset is investigated analytically. The output buffer converts the output signal from RZ to NRZ for further processing. The receiver is fabricated in an OPTO ASIC 0.35 μm CMOS technology and validated with an edge-emitting laser source at λ = 635 nm, achieving sub-μW average optical power operation with a sensitivity of -31.4 dBm at 200 Mbit/s (BER = 10 -9 , extinction ratio corrected for ∞). The power consumption is 1.25 mA, drawn from a single 2.5 V supply.

A multiplexer circuit that is capable of accessing 32 internal nodes for the continuous-time probing of signal waveforms is proposed. A chip has been fabricated with eight multiplexer instances and used in experiments for monitoring radiation-induced single-event transients in digital circuits. Pulses with a width of less than 100 ps and pulses over 1 V in height were observed for 230-MeV particle hits. Measurements show 8.5 GHz, −3-dB bandwidth, and a 1.92% total harmonic distortion for a 1-V input range, and a 6.58% total harmonic distortion for a 2-V input range. The measured dynamic range is nominally 26.5 dB.

A fully integrated single-photon avalanche diode (SPAD) using a controllable fast mixed quenching and active resetting circuit (QRC) fabricated in a $0.35-\mu\mathrm{m}$ high-voltage CMOS process is presented in this paper. The QRC features a fast active quenching time of 0.52 ns and a minimum dead-time of 4.57 ns, which corresponds to a maximum count rate of 218 Mcps. To validate the quenching performance, the circuit was integrated together with a large-area SPAD having an active diameter of $90\ \mu\mathrm{m}$ with a capacitance of 150 fF. A pad for a pico-probe was integrated on the chip, leading to a total capacitive load of 275 fF in SPAD cathode's node during transient measurements.

This paper presents ring modulator driver and receiver circuits designed for three-dimensional photonic–electronic integration using interwafer connections, whose parasitic capacitance is expected to be in the order of 15 fF. Both transmitter and receiver can operate with binary and PAM-4 modulation at 10 Gb/s. To the authors knowledge, it is the first PAM-4 ring modulator driver being presented. The circuits are designed in AMS 0.35-μm SiGe BiCMOS technology with total power consumptions of 160 and 180 mW for transmitter and receiver, respectively. The receiver's sensitivity is –27 dBm for binary and –22 dBm for 4-PAM signals both at a photodiode responsivity of R = 0.9 A/W. A monitor transimpedance amplifier with sensitivity –32 dBm was also designed in order to control the operating point of the ring modulator.

This paper reports the performances of a silicon photonics optical switch matrix fabricated by using large-scale three-dimensional (3-D) integration. The wavelength selective optical switch consists of a photonic integrated circuit (PIC), with 1398 circuit elements, interconnected in a 3-D stack with its control electronic integrated circuit (EIC). Each PIC element can be trimmed or reconfigured by using metallic heaters. The EIC is designed to drive the heaters and to read the signal of monitor photodiodes integrated into the PIC. Small footprint and high energy efficiency are achieved in the PIC and the EIC. Automatic wavelength alignment of the optical circuits in the PIC to the ITU grid and fine temperature tuning of each photonic element to optimize the switch insertion losses are obtained by an optimization routine. A fully packaged switch with input/output fibers is tested both for optical and electrical characteristics as well as for the system performances. Fiber-to-fiber insertion losses of about 20 dB and channel isolation of −35 dB are achieved. Bit error rate characteristics at 25 Gb/s are evaluated. Perspective applications of the optical switch in optical transport and intra-data center networks are discussed.

A silicon Single-Photon-Avalanche-Diode (SPAD) with $50\boldsymbol{\mu} \mathbf{m}$ diameter and 28.7V breakdown voltage was bonded to an integrated gating circuit (gater) to determine the avalanche transient experimentally at 25°C. The gater was clocked with 15MHz and avalanche pulses were measured with a fast active picoprobe. For an excess bias of 5.1V a mean fall time (of the cathode potential from 80% to 20%) of 10.3ns $(\boldsymbol{\sigma}=0.67\mathbf{ns})$ was obtained for photons from a halogen light source. The gater consists of cascode switches to achieve excess bias voltages up to 6.6V. Gater and SPAD were fabricated in the same $3.3\mathbf{V}/0.35\boldsymbol{\mu}\mathbf{m}$ CMOS technology.

Single-event transients (SETs) in a PIN photodiode and a single-photon avalanche diode (SPAD), both fabricated in the same 0.35μm CMOS process, are compared under heavy ion irradiation. The experimental results suggest that mainly the low-doped epitaxial layer defines the amount of collected charge. High current peaks at the output of the photodetectors, necessitate precautions in the quencher and read-out circuit design.

This paper presents an eight-channel optical transmitter and receiver circuit fabricated in 0.35 µm SiGe BiCMOS and integrated via inter-wafer connections to a photonic circuit fabricated in 220 nm SOI photonic technology in a 200 mm CMOS foundry. Measurement results demonstrate 8×l Gb/s for transmitter and 8×10 Gb/s for the receiver. The transmitter's extinction ratio is 5 dB. The receiver shows a sensitivity of −8.5 dBm at 10 Gb/s and a BER of 10–9, with a significant margin for improvement by optimizing the grating coupler efficiency, by a better fiber coupling, and to a lower extent by better matching the output impedance of the circuit.

We demonstrate the automatic thermal alignment of photonic components within an integrated optical switch. The WDM optical switch involves switching elements, wavelength de-multiplexers, interleavers and monitors each one needing independent control. Our system manages rerouting of channels coming from four different directions, each carrying 12, 200GHz spaced, wavelengths into eight add/drop ports. The integrated device includes 12 interleavers, which can act either as optical de-interleavers to split the optical signal into odd and even channels or as optical interleavers that recombine the odd and even channels coming from the switching matrix. Integrated Ge photodiodes are placed in key positions within the photonic integrated circuit (PIC) are serve for monitoring. An electronic integrated circuit (EIC) drives the photonic elements by means of dedicated heating circuits (824 on-board heater control cells, 768 for the switching elements and 56 for the interleavers and the mux/de-mux) and reads out the Ge diodes photocurrent through TIAs. We applied a stochastic optimization algorithm to align the spectral response of the interleavers to the ITU grid. We exploit the thermo-optic effect to shift the interleavers pass-band in a desired spectral position. The interleavers are provided with dedicated metallic heaters that can be operated in order to tune the interleaver response, which is typically misaligned due to fabrication inaccuracies. The experimental setup is made of a tunable laser coupled with one input port of optical switch. The optimization algorithm is implemented via a software to drive the EIC till finding the best heating configuration (on the two branches of the interleaver) on the basis of the monitor diode-feedback. This way, the even and odd wavelengths input in the interleaver are directed toward the wanted lines within the switching matrix. Our method has been used for aligning the micro-ring based switching elements in the PIC as well. In that case, the integrated Ge photodiodes have been used to align the photonic components in the PIC in order to enable different pathways for the routing or the broadcasting operation of the optical switch. With no bias applied to the heaters of the switching elements, the optical signal is expected to be maximum at the through port. When the micro-ring heaters are biased, the feedback controller finds the best set of heating values that minimize the optical power at the through port of the switching node. This way, the optical signal is coupled in the drop port and the node is enabled for switching. The algorithm, implemented in LabVIEW, converges over multiple instances and it is robust against stagnation. This work aims at enabling the automatic reconfiguration/restoration of the whole WDW optical switch.

This paper presents a driver circuit intended for optical modulators based on 3D-integrated ring resonators. The circuit was designed in a 0.35μm BiCMOS technology and the measurements are performed on the electrical test chip. The driver delivers 3-V voltage swing while consuming 160 mW at a data-rate of 10 Gb/s. The driver is suitable for NRZ binary as well as PAM-4 modulation formats.

This paper reports the first multiphase implementation based on the recently proposed nonlinear average current control (NACC) for power-factor-correction and dc–dc converters. A multiphase boost dc–dc converter with control and low-side power switches integrated on the same die using the 0.35- $\mu $ m HV CMOS process is designed and introduced. The converter benefits from using analog current controllers that are very simple, insensitive to noise, and independent of converter and control design parameters. Multiphase operation effectively enables higher operating frequency (seen from the converter input and output), which in turn enables smaller reactive components to be selected. The converter is dedicated to supplying the electric vehicle auxiliary board net (12 V) from the photovoltaic cell stack input, allowing a maximum power of 40 W to be transferred at 500-kHz switching frequency of each phase (effectively at 1.5 MHz). Maximum power point tracking is performed as the converter global control at $\sim $ 7.5 kHz, while the inner control loops are based on NACC. Suitability of such hybrid converters for integration with active solar cells makes them favorable to be used as a solar range extender for electric/hybrid vehicles, making this a step forward toward a complete system miniaturization of solar regenerative energy solutions in automotive applications—solar-module-integrated dc–dc converters. Experimental measurements performed with a converter prototype including a chip based on 0.35- $\mu $ m HV triple-well CMOS technology verify the proposed multiphase operation and NACC control method.