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Range performance of an imaging system is a key factor for an infrared search and tracking system with a purpose of detection, recognition and identification. Therefore, the prediction of the expected range performance is of utmost importance. The range prediction includes many variables that affect the outcome. Wavelength is one of the most important parameters because it has an enormous effect on range, but detector technology directly related to range performance. In this study, MWIR and LWIR imaging systems in certain configurations are modelled and analyzed in terms of range. The imaging system is modelled taking into account the properties of the detector and the optics, while the atmospheric conditions is modelled using MODTRAN. Analytical expressions for detection, recognition and identification ranges with respect to Johnson criteria for different target types are derived. The effects of the given parameters to the range performance are examined and a comparison between the different wavelengths is discussed.

In this work, a MOS memory with 4.56-nm ultrathin Al2O3-TiO2 nanolaminates thin film deposited by Atomic Layer Deposition (ALD) followed by 1-nm HfO2 tunnel oxide deposited by Plasma-Assisted ALD is studied. The charge trapping layer consists of 2.85-nm Si-nanoparticles (Si-NPs). A memory effect is observed using high frequency C-V measurements. The shift of the threshold voltage (Vt) obtained from the hysteresis measurements at 10/−10 V program/erase voltage is around 5 V and a 3 V Vt shift is obtained at low operating voltage of 6/−6 V. In addition, the calculated retention characteristic of the charges in the Si-NPs memory (>10 years) makes such memory structure promising for applications in non-volatile memory devices.

In this work, the effect of using a double layer of high-κ tunnel oxides Al2O3/HfO2 instead of a single layer Al2O3 in MOS memory with ZnO charge trapping layer is studied. A memory effect due to charging in the ZnO layer is observed using high frequency C-V measurements. The shift of the threshold voltage (Vt) obtained from the hysteresis measurements at 10/−10 V program/erase voltage is around 3.3 V with single layer tunnel oxide while 7 V with the double layer tunnel oxide with same total oxide thickness. In addition, the memory structures show long retention times (>10 years) which make them promising for applications in non-volatile memory devices. Moreover, the results highlight that tunnel band engineering can be used to further reduce the operating voltage and equivalent oxide thickness of future memory devices without sacrificing the memory performance.

In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics. Electronic supplementary material The online version of this article (doi:10.1186/s11671-015-0957-5) contains supplementary material, which is available to authorized users.

Date of Conference: 7-12 February 2015 Conference name: SPIE OPTO, 2015 - Proceedings - Silicon Photonics X We demonstrate Silicon-only near-infrared (NIR) photodetectors (sensitive up to 2000 nm) that meet large-scale ultralow-cost fabrication requirements. For the detection of infrared photons, we use metal nanoislands that form Schottky contact with Silicon. NIR photons excite plasmon resonances at metal nanoislands and plasmons decay into highly energetic charge carriers (hot electrons). These hot electrons get injected into Silicon (internal photoemission), resulting in photocurrent. Several groups have studied plasmonic nanoantennas using high resolution lithography techniques. In this work, we make use of randomly formed nanoislands for broad-band photoresponse at NIR wavelengths. We observe photoresponse up to 2000 nm wavelength with low dark current density about 50 pA/μm2. The devices exhibit photoresponsivity values as high as 2 mA/W and 600 μA/W at 1.3 μm and 1.55 μm wavelengths, respectively. Thin metal layer was deposited on low-doped n-type Silicon wafer. Rapid thermal annealing results in surface reconstruction of the metal layer into nanoislands. Annealing conditions control the average size of the nanoislands and photoresponse of the devices. An Al-doped Zinc Oxide (AZO) layer was deposited on the nanoislands using thermal atomic layer deposition (ALD) technique to acts as a transparent conductive oxide (TCO) and patterned using photolithography. AZO film creates electrical connection between the nanoislands and also makes a heterojunction to Silicon. Simple and scalable fabrication on Si substrates without the need for any sub-micron lithography or high temperature epitaxy process make these devices good candidates for ultra-low-cost broad-band NIR imaging and spectroscopy applications. © 2015 SPIE.

In this work, we propose Silicon based broad-band near infrared Schottky barrier photodetectors. The devices operate beyond 1200 nm wavelength and exhibit photoresponsivity values as high as 3.5 mA/W with a low dark current density of about 50 pA/mu m(2). We make use of Au nanoislands on Silicon surface formed by rapid thermal annealing of a thin Au layer. Surface plasmons are excited on Au nanoislands and this field localization results in efficient absorption of sub-bandgap photons. Absorbed photons excite the electrons of the metal to higher energy levels (hot electron generation) and the collection of these hot electrons to the semiconductor results in photocurrent (internal photoemission). Simple and scalable fabrication makes these devices suitable for ultra-low-cost NIR detection applications.

Innovative means to reduce the operating voltage and increase the stored charge density in current non-volatile memory devices are imperative [1-5]. In this work, 2.85-nm Si nanoparticles (Si-NPs) embedded in an ultrathin HfO2 layer are investigated for charge storage in low-cost non-volatile charge trapping memory devices. The memory hysteresis at different gate voltages, the stored charge, and the energy band diagram of the memory structure are analyzed. The memory cells are fabricated on an n+-type (111) (Antimony doped, 15-20 mΩ-cm) Si wafer. 5-nm-thick tunnel oxide Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system. Then, 1-nm-thick HfO2 is deposited by Plasma Assisted ALD at 195°C in an Oxford FlexAL system. Next, 2.85-nm Si-NPs are spin coated on the sample [6]. Again, a 1-nm-thick HfO2 is deposited by plasma assisted ALD at 195°C. Finally, an 8-nm-thick Al2O3 blocking oxide is deposited by ALD at 250°C. A 400-nm-thick Al layer for the gate contact is e-beam evaporated using a shadow mask with 10 μm feature size which eliminated the need for lithography steps. A cross-sectional illustration of the fabricated memory device is depicted in Fig. 1. The fabricated memory devices are electrically characterized by measuring the high frequency (1 MHz) C-Vgate characteristics of the programmed and erased states. Using the Agilent B1505A Semiconductor Device Parameter Analyzer, the memory cells gate voltage was first swept from -6 V forward to 6 V then backwards. A 1.8 V threshold voltage (Vt) shift is observed. The C-V measurements are repeated at a gate sweeping voltage of 8/-8 V and both erased and programmed states shifted outwards as shown in Fig. 2 resulting in a 4.5 V memory window. This indicates that the charge trapping layer is storing mixed charges: electrons and holes, however, more charging is due to holes revealed by the greater shift of the erased state in the negative direction as shown in Fig. 2. Moreover, the Vt shift is measured at different gate sweeping voltages as sown in Fig. 3 and the charge trapping density in the Si-NPs is calculated [3] and found to be 2.32 ×1013 cm-3. The analysis of the energy band diagram shows that the conduction band offset between Si and tunnel oxide is smaller than the valence band offset (ΔEC = 2.44 eV < ΔEV = 3.24 eV), thus the electrons tunneling probability is expected to be higher. However, the conduction band offset between the 2.85-nm Si-NPs [7] and tunnel oxide is much smaller than the valence band offset (ΔEC = 1.29 eV << ΔEV = 3.77 eV). This means that stored electrons can tunnel back to the Si channel much easier than holes. This confirms the observed larger charging due to holes in Fig. 2. Moreover, the addition of the high-dielectric constant (қ=20) HfO2 layer is expected to reduce the leakage of stored charges. Finally, the fabrication of such memory structure is compatible with existing semiconductor processing thus has potential on low-cost integrated nanoscale memory applications. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815. References [1] N. El-Atab, A. Ozcan, S. Alkis, A. K. Okyay, and A. Nayfeh "Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission", Appl. Phys. Lett. 104, 013112, 2014. [2] Nazek El-Atab, Ayse Ozcan, Sabri Alkis, Ali K. Okyay, and Ammar Nayfeh, “Silicon Nanoparticle Charge Trapping Memory Cell,” Phys. Status Solidi RRL. 8, 629, 2014. DOI: 10.1002/pssr.201409157 [3] Nazek El-Atab, Furkan Cimen, Sabri Alkis, Ali K. Okyay and Ammar Nayfeh "Enhanced memory effect with embedded graphene nanoplatelets in ZnO charge trapping layer," Appl. Phys. Lett. 105, 033102, 2014. [4] Nazek El-Atab, Furkan Cimen, Sabri Alkis, Bülend Ortaç, Mustafa Alevli, Nikolaus Dietz, Ali K. Okyay and Ammar Nayfeh "Enhanced memory effect via quantum confinement in 16 nm InN nanoparticles embedded in ZnO charge trapping layer," Appl. Phys. Lett. 104, 253106, 2014. [5] Nazek El-Atab, Ayman Rizk, Ali K. Okyay, Ammar Nayfeh, “Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer,” AIP advances 3, 112116, 2013. [6] G. Belomoin, J. Therrien, A. Smith, S. Rao, S. Chaieb, M. H. Nayfeh, "Observation of a magic discrete family of ultrabright Si nanoparticles," Appl. Phys. Lett. 80, 841, 2002. [7] O. M. Nayfeh, Ph.D dissertation, EECS, MIT, Cambridge, MA 2009. Figure 1