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77 results on '"Berekovic, M."'

7. Evaluating CMPs and their memory architecture

Author

Jesshope, C., Lankamp, M., Zhang, L., Berekovic, M., Müller-Schloer, C., Hochberger, C., Wong, S., and System and Network Engineering (IVI, FNWI)

Subjects
020203 distributed computing, Cellular architecture, Computer science, CPU cache, Locality, Cache-only memory architecture, Register file, Uniform memory access, 02 engineering and technology, Thread (computing), Memory map, 020202 computer hardware & architecture, Microarchitecture, Non-uniform memory access, Shared memory, Computer architecture, Memory architecture, 0202 electrical engineering, electronic engineering, information engineering, Interleaved memory, Memory protection
Abstract

Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of technology. This paper presents a CMP architecture that supports automatic mapping and dynamic scheduling of threads leaving the binary code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this abstract processor architecture is the memory system. This paper evaluates the memory architectures, which must maintain performance across a range of targets.

Published
2009

8. Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP

Author

Govers, J., Huisken, J., Berekovic, M., Rousseaux, O., Bouwens, F., de Nil, M., van Meerbergen, J., Stenström, P., Dubois, M., Katavenis, M., Gupta, R., Ungerer, T., and Electronic Systems

Abstract

Impulse Radio-based Ultra-Wideband (UWB) technology is a strong candidate for the implementation of ultra low power air interfaces in low data rate sensor networks. A major challenge in UWB receiver design is the low-power implementation of the relatively complex digital baseband algorithms that are required for timing acquisition and data demodulation. Silicon Hive offers low-power application specific instruction set processor (ASIP) solutions. In this paper we target the low-power implementation of an UWB receiver’s digital baseband algorithm on an ASIP, based on Silicon Hive’s solutions. We approach the problem as follows. First we implement the algorithm on an existing ASIP and analyze the power consumption. Next we apply optimizations such as algorithmic simplification, adding a loopcache and adding custom operations to lower the dissipation of the ASIP. The resulting ASIP consumes 0.98 nJ (with a spreading factor of 16) per actual data bit, which is lower than an existing application specific integrated circuit (ASIC).

Published
2008

9. Image Quantisation on a Massively Parallel Embedded Processor

Author

Jacobs, J.W.M., van Engelen, Leroy, Kuper, Jan, Smit, Gerardus Johannes Maria, Vassiliadis, S., Berekovic, M., and Hamalainen, T.D.

Subjects
Markov random field, Parallelism (rhetoric), Exploit, METIS-242199, Computer science, Process (computing), Pentium, Image processing, IR-61928, Parallel computing, EWI-11094, Massively parallel, Image (mathematics)
Abstract

Developing code for SIMD type hardware architectures often is a tedious job. This is caused by the absence of both a coherent methodological framework and a hardware independent tooling. Besides, the inherently difficult nature of programming dedicated massively parallel embedded processors, complicates the matter. This paper describes the quest for collecting and shaping the necessary methodological parts into a single framework called IRIS. This framework is illustrated by a concrete case "Stochastic Image Processing". IRIS is based on an incremental construction of executable representations, which converge to the final target language implementation in a semi-automated way.

Published
2007

10. Design of 100 muW wireless sensor nodes on energy scavengers for biomedical monitoring

Author

Yseboodt, L., de Nil, M., Huisken, J., Berekovic, M., Zhao, Q., Bouwens, F., van Meerbergen, J., Vassiliadis, S., Berekovíc, M., Hämäläinen, T.D., Electrical Engineering, and Electronic Systems

Abstract

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. We aim for less than 100μW power consumption as that is the power energy scavengers can deliver. We follow a bottleneck-driven approach, the following steps are applied: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of around 11μW is possible for both radio and DSP with the electrocardiogram algorithm.

Published
2007

12. Design of 100 muW wireless sensor nodes for biomedical monitoring

Author

Yseboodt, L., de Nil, M., Huisken, J., Berekovic, M., Zhao, Q., Bouwens, F., Hulzink, J., van Meerbergen, J., Yseboodt, L., de Nil, M., Huisken, J., Berekovic, M., Zhao, Q., Bouwens, F., Hulzink, J., and van Meerbergen, J.

Abstract

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. The target power consumption is 100 μW as that is the power energy scavengers can deliver. We follow a bottleneck-driven approach: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of 11 μW is possible for both radio and DSP running the electrocardiogram algorithm.

Published
2009

14. Secure, Mobile Visual Sensor Networks Architecture

Author

Ladis, E., primary, Papaefstathiou, I., additional, Marchesani, R., additional, Tuinenbreijer, K., additional, Langendorfer, P., additional, Zahariadis, T., additional, Leligou, H. C., additional, Redondo, L., additional, Riesgo, T., additional, Kannegiesser, P., additional, Berekovic, M., additional, and van Rijn, C. J. M., additional

Published
2009
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23. ADRES & DRESC: Architecture and Compiler for Coarse-Grain Reconfigurable Processors.

Author

Vassiliadis, Stamatis, Soudris, Dimitrios, Mei, B., Berekovic, M., and Mignolet, J-Y.

Abstract

Nowadays, a typical embedded system requires high performance to perform tasks such as video encoding/decoding at run-time. It should consume little energy to work hours or even days using a lightweight battery. It should be flexible enough to integrate multiple applications and standards in one single device. Coarse-grained reconfigurable architectures (CGRAs) are emerging as potential candidates to meet the above challenges. Many of them were proposed in recent years. However, existing CGRAs have yet been widely adopted mainly because of programming difficulty for such complex architecture In this chapter, a novel CGRA, ADRES (architecture for dynamically reconfigurable embedded systems), and a compiler framework, DRESC (dynamically reconfigurable embedded system compiler), are presented to address issues of existing CGRAs. Our approach possesses several unique features. First, the ADRES architecture tightly couples a very-long instruction word (VLIW) processor and a coarse-grained array by providing two functional views on the same physical resources. It brings advantages such as high performance, low communication overhead and easiness of programming. Second, the DRESC framework introduces software-like design experience. An application written in C can be quickly mapped onto an ADRES instance. The key technology behind the DRESC framework is a novel modulo scheduling algorithm, which can pipeline a loop onto the partially interconnected array to achieve high parallelism. Finally, ADRES is a template instead of a concrete architecture. With the retargetable compilation support from DRESC, architectural exploration becomes possible to discover better architectures or design domain-specific architectures A number of multimedia and telecommunication kernels are mapped. The instruction-per-cycle (IPC) up to 42.7 has been observed on an 8 × 8 ADRES instance. A multimedia application, MPEG-2 decoder, is mapped within one week starting from a software implementation. The speed-up over an 8-issue VLIW are about 12 times for kernels and 5 times for the entire application. [ABSTRACT FROM AUTHOR]

Published
2007
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