101 results on '"Benoît Dupont de Dinechin"'
Search Results
2. In-Place Multicore SIMD Fast Fourier Transforms.
3. Exact Fused Dot Product Add Operators.
4. A Posit8 Decompression Operator for Deep Neural Network Inference.
5. Computing In-Place FFTs with SIMD Lane Slicing.
6. Distortion Approximation of a Compressed Softmax Layer.
7. A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory.
8. Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities.
9. Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip.
10. Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures.
11. A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore.
12. Parallel code generation of synchronous programs for a many-core architecture.
13. Network-on-chip service guarantees on the kalray MPPA-256 bostan processor.
14. Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
15. Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor.
16. Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors.
17. Asynchronous one-sided communications and synchronizations for a clustered manycore processor.
18. Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
19. DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems.
20. Engineering a Manycore Processor for Edge Computing.
21. Optimal and fast throughput evaluation of CSDF.
22. Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor.
23. The shift to multicores in real-time and safety-critical systems.
24. MPI communication on MPPA Many-core NoC: design, modeling and performance issues.
25. Implementation of a Fast Fourier transform algorithm onto a manycore processor.
26. Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources.
27. Guaranteed Services of the NoC of a Manycore Processor.
28. Time-critical computing on a single-chip massively parallel processor.
29. Using the SSA-Form in a Code Generator.
30. Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor.
31. Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks.
32. Periodic schedules for Cyclo-Static Dataflow.
33. A clustered manycore processor architecture for embedded and accelerated applications.
34. A Distributed Run-Time Environment for the Kalray MPPA®-256 Integrated Manycore Processor.
35. Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor.
36. K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph.
37. A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs.
38. A mixed-precision fused multiply and add.
39. Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus.
40. Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency.
41. Converging to periodic schedules for cyclic scheduling problems with resources and deadlines.
42. Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors.
43. Fast liveness checking for ssa-form programs.
44. SCAN: A Heuristic for Near-Optimal Software Pipelining.
45. Division by Constant for the ST100 DSP Microprocessor.
46. Scheduling an interval ordered precedence graph with communication delays and a limited number of processors.
47. A Qualitative Approach to Many‐core Architecture
48. Efficient liveness computation using merge sets and DJ-graphs.
49. Code generator optimizations for the ST120 DSP-MCU core.
50. Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.