Search

This article presents a compact model for the drain current and capacitances of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). The model is valid in the deep and tail states regions of operations, with a smooth transition between the two. The model parameters were extracted independently in the two regions using the unified model and extraction method (UMEM). The subthreshold regime and series resistances are considered for the drain current modeling. For the capacitances, it was found that the bias-dependent parasitic capacitances play a dominant role. The model was validated with TCAD simulations, with very good agreement.

In this work, we explore the output-conductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the current-voltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

We target the parameter extraction from ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics and modeling of organic thin-film transistors (OTFTs) from 150 K up to 350 K (in two different manufacturing technologies). We also analyze the temperature dependence of the extracted parameters. For that purpose, we used a unified model and parameter extraction method at different temperatures adapted to OTFTs. We validated our model by comparison with experimental ${I}$ – ${V}$ characteristics in both the linear and saturation regimes and ${C}$ – ${V}$ characteristics at different frequencies.

In this work, short-channel effects (SCEs) in cylindrical gate-all-around (GAA) MOSFETs with intrinsic or lightly doped channels are analytically described by using the conformal mapping technique for 2-D double-gate (DG) FETs. An equivalent capacitor model leads to an equivalent channel length concept, which allows to correctly determine the SCEs relevant center and surface potentials ( $\Phi _{{C}} $ and $\Phi _{{S}} $ ) at the potential barrier. Furthermore, we make use of the rotational symmetry of GAA FETs and modify a compact drain current model of a DG device to use it for GAA transistors. Also, a mathematical correlation regarding quantum confinement for thin body transistors is derived, which shows that the mostly unwanted quantum effects occur in GAA structures already for thicker channels compared to DG transistors. Both transistor types experience a comparable influence with regard to quantization if the channel thickness of GAA FETs is 53% more than that of DG FETs. The dc behavior of our adapted model is verified with 3-D TCAD simulation data and applied to experimental data of ultrascaled silicon on insulator (SOI) omega-gate nanowire N-MOSFETs.

In this study, a consistent analytical charge-based model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-number-fluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

A charge-based macromodel for small-signal ac and transient analyses of organic thin-film transistors (TFTs) is presented. Due to the comparatively small charge-carrier mobility in organic TFTs, the dynamic behavior of the gate-field-induced carrier channel is greatly affected by the frequency of the applied gate–source and drain–source voltages. The model presented here is, therefore, based on the transmission-line model and shown to reproduce the results of frequency-dependent admittance measurements and numerical simulations of the transient switching behavior of organic TFTs fabricated in the staggered architecture with good accuracy. The model has been implemented in the hardware description language Verilog-A.

This article introduces analytical compact models of short-channel effects in staggered organic thin-film transistors (TFTs). The effects of subthreshold-swing degradation, threshold-voltage roll-off, and drain-induced barrier lowering (DIBL) on the static current-voltage characteristics of staggered TFTs are extracted from an analytical potential solution of the 2-D problem of the staggered geometry. This solution is derived by using the Schwarz–Christoffel transformation that leads to a complex mapping function linking the staggered geometry to an equivalent in another coordinate system for which an analytical potential solution exists. The technology CAD (TCAD) Software Sentaurus is used to verify the compact models. Finally, the closed-form and physics-based equations are incorporated into an existing compact current model and verified by measurements on staggered organic TFTs with channel lengths as small as 0.4 $\mu \text{m}$ fabricated on flexible plastic substrates by stencil lithography.

This article presents an analytical model to reproduce the ${I}-{V}$ characteristics of a double-gate (DG) amorphous indium–gallium–zinc oxide (a-IGZO) TFT with symmetric structure. This model for the above-threshold region is based on the gate voltage dependence of surface potential and potential at the center of the semiconductor layer, which are described by analytical expressions. Considering the densities of the free and localized carrier in the semiconductor, the total carrier density, which is equal to the effective carrier density, is calculated. The carrier mobility, calculated as the ratio between the free carrier and the effective carrier density, depends on the gate voltage as a power law with the power parameter $\gamma $ different from zero, as it is typically represented for the amorphous TFT. The drain current model has only 13 model parameters and was validated with six different simulated transistor structures, as well as with an experimental device. A good coincidence of the modeled characteristics with both the simulated and experimental devices was obtained.

This journal paper introduces a charge-based approach for the calculation of charges and capacitances in staggered organic thin-film transistors (OTFTs). Based on an already existing DC model, the charges are yielded in an analytical and compact form. A linear charge partitioning scheme is applied to ascribe charges to the drain/source side of the channel. The final equation is only dependent on geometrical parameters and the charge densities at the drain/source end of the channel. Furthermore, the fringing regions in fabricated devices are taken into account. The compact model is implemented in Verilog-A and the capacitances are compared to Sentaurus TCAD simulation results as well as measurement data. Additionally, simulation results for a differential amplifier are compared to measurements. The advantage of this model is its unique formulation covering all operation regimes.

In this review, recent advances in compact modeling of organic field-effect transistors (OFETs) are presented. Despite the inherent strength for printed flexible electronics and the extremely aggressive research conducted over more than three decades, the OFET technology still seems to remain at a relatively low technological readiness level. Among various possible reasons for that, the lack of a standard compact model, which effectively bridges the device- and system-level development, is clearly one of the most critical issues. This article broadly discusses the essential requirements, up-to-date progresses, and imminent challenges for the OFET compact device modeling toward a universal, physically valid, and applicable description of this fast-developing technology.

In this paper, the flicker noise properties of bottom-gate ESL structured amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) from two different technologies have been studied and modeled. Model development is carried out by adapting the Unified Model parameter Extraction Method (UMEM), developed for parameter extraction and compact modeling of TFT devices, and the unified 1/f noise model. Furthermore, comparative study of device figures of merits is performed to point out the device performance enhancements that the different fabrication technologies have brought about. It is found out that both devices have low deep state density, whereas the second device demonstrated higher performance in terms of carrier mobility and subthreshold slope. Both the DC and noise models are validated by matching them against experimental data obtained in different regimes of device operation.

This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore, a Special Issue was needed to present recent compact modeling solutions for semiconductor devices

In this article, we present the analysis of the nonlinear harmonic distortion (HD) characteristics for two kinds of amorphous oxide semiconductor thin film transistors (AOSTFTs) based on SiO2/indium–gallium–zinc oxide (IGZO) and HfO2/hafnium–indium–zinc oxide (HIZO), applying the integral function method (IFM). An analysis of the distortion of the transistors used as quasi-linear resistor and the variation in HD as a function of the parameter ${g}_{m}/{I}_{\text {DS}}$ are also included. As far as we know, this kind of study has not been reported before. It is shown that parameter HD2 does not present a minimum as in MOSFETs, because the transfer characteristic does not present an inflection point. The value of HD2 is higher than that of HD3 in the whole operating ranges. When the transistor is used as quasi-linear resistor for different ${V}_{G}$ bias, HD2 is greater than HD3 in more than 50 dB. Because HD2 is significantly greater than HD3, the total HD (THD) parameter can be considered practically equal to HD2. In addition, the behavior of HD around the low-power operating region is shown.

The variability of the electrical characteristics of current-mirror circuits based on organic thin-film transistors is analyzed using experimental data obtained from a large number of discrete transistors and from a large number of current mirrors fabricated on a flexible polymeric substrate. Depending on the channel length of the transistors (5 μm or 2 μm) and on whether the two transistors comprising the current mirror are biased simultaneously or separately, the drain-current mismatch of the current mirrors is as small as 1% and as large as 25%.

In this paper, a charge-based analytical model for intrinsic capacitances in tunnel field-effect transistors (TFETs) is presented. The model is derived for a Si Double-Gate (DG) n-TFET whose flexibility is applicable to single-gate or p-type TFETs as well. The model is verified comparing with the TCAD simulations as well as measurements data. Considering the capacitances of fabricated Si planar p-TFETs on Ultrathin Body, some deviations between TCAD simulations, compact model and measurements are observed. Here the effect of Schottky barriers at NiSi2 contacts are analyzed and a theory for the reason associated deviations and the unexpected behavior of intrinsic capacitances is evolved. Furthermore, a technique to include this effect in the aforementioned model is also presented.

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

A full capacitance model for Amorphous Oxide Semiconductor Thin Film Transistors (AOSTFTs), considering the effect of the drain contact overlap in bottom gate passivated structures is presented. It is shown that this drain overlap, on top of the passivation layer, serves as a second gate with an applied voltage equal to VDS. When VDS > VT the semiconductor-passivation (S-P) interface will be in accumulation and the behavior of the different capacitance is affected. An expression to represent this effect is included in the present model. The overlap capacitance between gate and drain/source, as well as the effect of reducing the channel capacitance as the drain is increased, are also considered by the model. The calculated capacitance is a function of the threshold voltage, (VT), the mobility and saturation parameters (γa ,αs), and the sharpness of the knee region m, which are extracted using the Unified Model and Extraction Method (UMEM) for AOSTFTs. Results are compared with simulated and experimental data.

We present a new complete capacitance model for the amorphous indium-gallium-zinc-oxide (IGZO) thin-film-transistor (TFT), valid in the above-threshold and subthreshold regime (Fermi level in the tail and deep states, respectively). The parameters applied in the model are analytically extracted from the current–voltage characteristics of the devices, using a previously developed unified model and parameter extraction method. The good agreement between our capacitance model and 3D numerical TCAD simulations proves the validity of this letter, which is expected to be useful for the optimization of fabrication processes and for the prospective estimation of the effect of process conditions on circuit performances.

This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter.

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

We present analytical physics-based compact models for the Schottky barriers at the interfaces between the organic semiconductor and the source and drain contacts in organic thin-film transistors (TFTs) fabricated in the coplanar and the staggered device architecture, and we illustrate the effect of these Schottky barriers on the current-voltage characteristics of the TFTs. The model for the source barrier explicitly takes into account the field-dependent barrier lowering due to image charges. Potential solutions have been derived by applying the Schwarz-Christoffel transformation, leading to expressions for the electric field at the source barrier and for the contact resistance at the source contact. With regard to the drain barrier, a generic compact-modeling scheme based on the current-voltage characteristics of a barrier-less TFT is introduced that can be applied to any compact dc model. Finally, both models are incorporated into an existing charge-based compact dc model and verified against the results of measurements performed on coplanar and staggered organic TFTs with channel lengths ranging from 0.5 μm to 10.5 μm.

This paper presents a closed-form, physics-based compact model which is used to calculate the DC characteristics of double gate Schottky barrier field-effect transistors (SBFETs) and reconfigurable field-effect transistors (RFETs). Therefore, the model calculates the drain current which consists of field emission through the Schottky barrier and thermionic emission over the barrier. In order to validate the model, this paper shows results for the calculated current in SBFETs and RFETs compared to transfer characteristics of simulated devices and measurements, which show a good agreement.

We target the analysis and modeling of the I-V characteristics in organic thin film transistors (OTFTs) and IGZO TFTs from 150K to 350K, as well as the temperature dependences of the extracted parameters. Our compact model reproduces very well the I-V characteristics within that range of temperatures for both types of devices.

We review recent compact modeling solutions for Organic and Amorphous Oxide TFTs (OTFTs and AOS TFTs, respectively), which were developed, under the framework of the EU-funded project DOMINO, to address issues specifically connected to the physics of these devices. In particular, using different approaches, analytical equations were formulated to model the Density of States (DOS), different transport mechanisms, trapping/de-trapping, drain current, stress, capacitances, frequency dispersion and noise. The final TFT models were, after implementation in Verilog-A, validated by means of the design and simulation of test circuits.

Previously, we proposed a new interpolation expression to bridge the transition between the linear and the saturation regimes of “intrinsic” MOSFET. This approach, in contrast to the traditional one, gives a monotonic decrease of the differential conductance from the maximum value in the linear regime to the minimum value in the saturation regime. Later, we proposed a linear approximation for an “extrinsic” MOSFET drain current dependence on the “extrinsic” drain bias in the saturation regime for not very high drain bias when nonlinear effects can be neglected. To obtain this approximation, an equation for the output differential resistance of the “extrinsic” MOSFET in saturation regime was obtained, that is similar to the result known from the theory of the common source MOSFET amplifier with source degeneration. In this paper, we combine these two results and present an “extrinsic” compact model for a short-channel MOSFET above threshold drain current with proper account of the differential conductance in the saturation regime.

A full capacitance model for amorphous oxide semiconductors Thin Film Transistors (AOSTFTs) is validated in dynamic regime using a Ring Oscillator of 19 stages fabricated and measured, describing the model in Verilog-A language. In this paper, we obtained good results and coincidence between the dynamic characteristics of the circuit measured and modeled. The modeled characteristics where obtained using the SmartSpice tool from Silvaco. The model includes the effect of the different overlaps capacitance present in the structures of the a-IGZO TFTs analyzed, which is an important factor used to determine the oscillator performance of the devices. We also analyze the dynamic behavior of the circuit when the internal capacitances of the TFTs increase or decrease, with respect to the real value, obtaining the expected behavior. In this work we also show how was considered the effect of the time in the internal capacitances of the transistors, using the Spice simulator. The model was validated for different supply voltages, for 10, 15 and 20 V, in all cases, the agreement between characteristics simulated and measured was good.