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The progressive mask defect problem is an industry-wide mask reliability issue. Even if masks are determined to be clean upon arrival from the mask supplier, some of these masks can show catastrophic defect growth over the course of production usage in the fab. The categories of defects that cause reticle-quality degradation over time are defined as progressive defects, commonly known as crystal growth, haze, fungus or precipitate. This progressive defect problem has been around for more than a decade and was observed at almost every lithographic wavelength. This problem is especially severe at 193nm lithography. Triggering the increased severity are shorter wavelength lithography - where the photons are highly energized - and the concurrent transition to 300 mm wafers, which require photomasks to endure more prolonged exposure as compared to 200 mm wafers. Both embedded phase shift masks (EPSMs) and chrome-on-glass masks are affected by progressive defects. These defects are generally found on the patterned surface underneath the pellicle (on clear, half-tone or chrome patterns), as well as on the backside surface of the masks. Past cases have indicated that this problem mainly starts on the scribes and borders, with emerging semi-transmissive contamination of ~100nm. These defects then propagate into the die area while growing in both size and opaqueness. Compositional analysis has shown that the majority of these defects are ammonium sulfate. However, since significant effort focused on the elimination of ammonium sulfate a new trend has emerged. Current studies show severe defect growth consists of organic contaminants (ammonium oxalate, cyanuric acid etc.) on half-tone edges and on chromium edges. The sources for progressive defect mechanisms are under investigation, though several candidates have been considered: maskmaking materials and process residues (mainly ammonium or sulfate ions), the fab environment, or the stepper environment. Controlling or balancing these sources may help to reduce the frequency at which these defects occur, but thus far has been unable to eliminate the problem. With each successive device shrink, the resultant changes in lithographic wavelength and processing within the mask fabrication facility and IC fab disrupt the fine balance among the above suspected defect sources, resulting in the return of catastrophic progressive defect growth. Due to this uncertainty, strict mask quality monitoring in the fab is essential. The ideal reticle quality control goal in a fab should be to detect any nascent progressive defects before they become yield limiting. Hence, the masks should be monitored on an established frequency that allows problem masks to be removed from production and sent for rework prior to impacting device performance and fab yield.

Progressive mask defect problems such as crystal growth or haze are key yield limiters for DUV lithography, especially in 300mm fabs. Even if the incoming mask quality is good, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught in advance during production in the fabs. The ideal reticle quality control goal should be to detect any nascent progressive defects before they become yield limiting. So, a high-resolution mask inspection is absolutely needed, but the big question is: “how often do fabs need to re-inspect their masks”? This re-inspection frequency should ideally be the most cost-effective frequency at which there is minimum threat for a yield loss. Previous work towards finding a cost effective mask re-qualification frequency was done prior to the above mentioned progressive defect problem that industry started to see at a much higher rate during just the last few years. Other related recent work was done 2004 BACUS conference which is dedicated to DRAM fab data. In this paper a realistic mask re-qualification frequency model has been developed based on a large volume of data from an advanced logic fab. This work will compliment previous work in this area done with the data from a DRAM fab. Statistical methods are used to analyze mask inspection and product data, which are combined in a stochastic model.

Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.

Dark field (i.e. hole and trench layer) lithographic capability is lagging that of bright field. The most common dark field solution utilizes a biased-up, standard 6% attenuated phase shift mask (PSM) with an under-exposure technique to eliminate side lobes. However, this method produces large optical proximity effects and fails to address the huge mask error enhancement factor (MEEF) associated with dark field layers. It also neglects to provide a dark field lithographic solution beyond the 130nm technology node, which must serve two purposes: 1) to increase resolution without reducing depth of focus, and 2) to reduce the MEEF. Previous studies have shown that by increasing the background transmission in dark field applications, a corresponding decrease in the MEEF was observed. Nevertheless, this technique creates background leakage problems not easily solved without an effective opaqueing scheme. This paper will demonstrate the advantages of high transmission lithography with various approaches. By using chromeless dark field scattering bars around contacts for image contrast and chromeless diffraction gratings in the background, high transmission dark field lithography is made possible. This novel layout strategy combined with a new, very high transmission attenuating layer provides a dark field PSM solution that extends 248nm lithography capabilities beyond what was previously anticipated. It is also more manufacturing-friendly in the mask operation due to the absence of tri-tone array features.

The future of mask industry technology is in flux. While the requirements for current and near-term lithographic capability is well understood, advanced lithography options pose a completely new set of challenges to the mask maker. Challenges are not only process and materials related, but also include more fundamental concerns dealing with how to afford the necessary capability development. This paper identifies the issues and attempts to propose solutions to the industry's growing concerns.

This study explores the capability of printing 100 nm contacts through the use of 9% and 15% attenuated phase shift masks and a 0.75 NA 193 nm scanner. The mask designs targeted simultaneous solutions for 100 nm contacts at pitches from 200 nm to 300 nm. The two masks were successfully manufactured from experimental MoSiON embedded-attenuated phase shift mask (EAPSM) blanks. The 100 nm contacts were successfully printed with a depth of focus (DOF) from 0.1-0.7 μm. Overlapping process windows were not achieved but were possible upon adjustment of the mask biases. The observed mask error enhancement factor (MEEF) was approximately 3 for the 220 nm pitch. Side lobe printing was not observed for either mask.

This work involved a demonstration of the infrastructure and the ability of mask-making equipment to produce 9 inch reticles. While the choices for this particular work made the timing and logistics long and complicated, we find that there currently exists adequate infrastructure to create 9 inch reticles and we have used this ability to produce several demonstration quality examples.

There are several different methods for printing contact holes on wafers using optical lithography. A preferred resolution enhancement technique for improved contact hole lithography performance is the embedded attenuated phase shift mask (EAPSM). The EAPSM comes in many flavors and forms, but the current preferred form is a film transmission of 6 percent and a phase shift of 180 degrees relative to the clear fused silica areas. It is important to note that the phase shift and transmission values for the phase shift mask are at the actinic exposure wavelength of the wafer stepper/scanner. That is the mask is designed to have a transmission of 6 percent and phase shift of 180-degrees at 248nm or 193nm, depending on the wafer stepper. The resulting transmission of the phase shift mask at the inspection tool wavelength of 365nm is much higher, and the phase shift of the 365nm radiation is significantly less than at the shorter actinic wavelength. The gray-scaled aerial images that are collected by the mask inspection tool could vary significantly for the same size 2-D feature in the binary mask, the 248nm EAPSM, and the 193nm EAPSM. This is also compounded by the fact that the inspection tool calibrates the background transmission of the phase shift material as 0 percent transmission and calibrates the transmission of the fused silica as 100 percent transmission. When these gray-scaled images are used in an energy flux algorithm for contact area measurement, they can be potentially different for each of the three types of masks used to print contact holes. This paper explores the issues involved in using an off-actinic aerial image as the basis for the AVI method of contact sizing.

The Chromeless Phase Shift Mask (CLM) approach from ASML MaskTools has been developed as an approach to achieve sub-100nm lithography using currently available stepper technology. The technology uses sub-resolution gray-scaled regions of zero-phase and pi-phase quartz on the mask to produce effective feature widths well below 100nm at the wafer. The features on the mask consist entirely of etched and unetched quartz. No features consist of chrome on the mask. The integration of this type of phase shift mask technology into the photomask-manufacturing environment requires that the mask manufacturer be able to inspect the mask for defects in the quartz. The Defect Sensitivity Monitor (DSM) pattern was used to construct a CLM mask. The mask was inspected using commercially available inspection platforms, and the resulting inspection capability is reported.

This paper examines the effects of mask printability of various OPC defect types on a MoSi APSM mask using an MSM-100 AIMS tool operating at 248nm as a printability prediction tool. Printability analysis will be used to address differences in intensity, image capture wavelength, defocus, defect size, type, and placement on two substrate materials. Defect correlation to photomask CD error, aerial image intensity error, and MEEF on high-end KrF photomasks will also be studied.

The manufacturing of advanced reticles for deep UV steppers has stressed the mask industry's writing, processing, inspection and repair capabilities. Meeting technology demands has been especially arduous for reticle defect inspection with the rapid evolution of both novel PSM materials and OPC geometries. Also, the switch to a 4x-reduction ratio and ever-lower k 1 wafer lithography has resulted in increased overall defect printability. To respond to these challenges, a new reticle inspection system with laser UV imaging has been evaluated and shown to achieve mask defect sensitivity of 150nm and below on DUV EA-PSM and OPC masks. The extension to UV wavelength improves image resolution, thus improving sensitivity and minimum linewidth capability. A description of the major changes made to the optics, algorithms, mechanics, and software is presented. Using both programmed defect test masks and actual production reticles, initial observations of the nature and frequency of defects detected were compared to the expected 150 nm sensitivity. Preliminary characterizations of this system included the number and types of defects captured at multiple pixel sizes. Comparisons with visible light systems illustrate the advantage of utilizing shorter wavelengths for reticle inspection. During the initial characterization of UV inspection performance, wavelength-specific defects were identified on advanced reticles that were not detected by visible light inspections. Examples of these defects and the physical mechanisms responsible for UV-specific defects will be discussed. The quality of defect review images has a direct impact on the effectiveness and ease-of-use of reticle inspection systems. The high quality, UV images available from the new system can be viewed in both normal and sharpened defect review displays which give the manufacturing operator better clarity for dispositioning sub-quarter-micron defects.

For obvious cost reasons, semiconductor manufacturers are constantly striving to produce ever smaller wafer geometries with the current installed base of wafer steppers. Many techniques (phase shifting, optical proximity correction, etc.) have been used successfully to 'squeeze' more resolution from these steppers than was once thought possible. Wafers processed using non-aggressive k 1 factors provided a linear correlation between mask and wafer feature sizes. However, it has been shown that pushing k 1 factors to very low levels causes a nonlinear response between changes in photomask and wafer critical dimension. This non-linearity demands extremely tight photomask CD control specifications. Total CD errors 50 nm and smaller can cause unacceptable wafer CD variation. Current high end reticle manufacturers are capable of meeting a total CD uniformity specification of approximately 40 nm as measured by sampling strategies using optical metrology tools. These tools are very useful for detecting macro changes in CD; however, they will only detect a localized error if it happens to occur precisely at the point of measurement. In contrast, a pattern inspection system employing a linewidth measurement algorithm can ensure detection of all localized errors within the detection and review capability of the system. The problem with reticle CD error detection capability is that there is a large discrepancy between currently available detection of greater than or equal to 150 nm and required detection of less than or equal to 50 nm necessary for proper wafer functionality at low k 1 lithography. In this paper, defect sensitivity and false detection performance of a new advanced line measurement algorithm was tested. The test vehicles included both an industry standard and a custom designed programed defect test mask. In addition, production masks with naturally occurring localized CD errors that caused wafer pattern bridging were analyzed. This new experimental algorithm has shown localized CD error detection of less than or equal to 100 nm reticle defects.

For obvious cost reasons, semiconductor manufacturers are constantly striving to produce ever smaller wafer geometries with the current installed base of wafer steppers. Many techniques (phase shifting, optical proximity correction, etc.) have been used successfully to 'squeeze' more resolution from these steppers than was once thought possible. Wafers processed using non-aggressive k 1 factors provided a linear correlation between mask and wafer feature sizes. However, it has been shown that pushing k 1 factors to very low levels causes a nonlinear response between changes in photomask and wafer critical dimension. This non-linearity demands extremely tight photomask CD control specifications. Total CD errors 50 nm and smaller can cause unacceptable wafer CD variation. Current high end reticle manufacturers are capable of meeting a total CD uniformity specification of approximately 40 nm as measured by sampling strategies using optical metrology tools. These tools are very useful for detecting macro changes in CD; however, they will only detect a localized error if it happens to occur precisely at the point of measurement. In contrast, a pattern inspection system employing a linewidth measurement algorithm can ensure detection of all localized errors within the detection and review capability of the system. The problem with reticle CD error detection capability is that there is a large discrepancy between currently available detection of greater than or equal to 150 nm and required detection of less than or equal to 50 nm necessary for proper wafer functionality at low k 1 lithography. In this paper, defect sensitivity and false detection performance of a new advanced line measurement algorithm was tested. The test vehicles included both an industry standard and a custom designed programmed defect test mask. In addition, production masks with naturally occurring localized CD errors that caused wafer pattern bridging were analyzed. This new experimental algorithm has shown localized CD error detection of less than or equal to 100 nm reticle defects.

For years equipment suppliers have opened their doors to evaluations by potential customers. Unfortunately, the only feedback a supplier received concerning its performance was a purchase order (or the lack of one). Neither was there any benchmarking against other suppliers' results to identify niche areas or spark necessary tool improvement programs. The result was an industry where new tool development projects ran the risk of being dictated by conjecture and assumption rather than a more empirical approach. This paper presents a method by which reticle inspection tools can be characterized more comprehensively. While grounded in common sense, some of the techniques used were considered quite unorthodox. By consulting the equipment supplier as to which test vehicles might best demonstrate its tool capability or might expose a weakness in the competitor's tool, topics that the customer might not otherwise have thought of were covered in the evaluation. Securing permission to feed back comprehensive results to all suppliers also guaranteed future focus on critical issues and limited development activities to only those deemed value-added by the customer. In addition, specific test battery topics were derived from consultations with semiconductor customers. The intent was to understand which reticle patterns and defect types were critical to the end user. The expected outcome after this type of evaluation is a quantified performance benchmark which facilitates industry-wide reticle inspection capability improvement over a shorter period of time.

As wafer fab technology proceeds into smaller images over larger field sizes, there is a need for tighter critical dimension (CD) uniformity and smaller allowable defect sizes. The maskmaker is required to reduce these sources of error as much as possible at the reticle level. As the lithography and process contributions are reduced, contribution from the mask blank itself becomes significant. Selection of the best vendor for optimum CD and defect performance becomes critical. Unfortunately, the best vendor for CD uniformity may not be the best for defect density on certain product types, and vice versa. An additional complication is that the most critical specifications are required over larger areas of 6 multiplied by .250 substrates which have not yet been optimized by blank suppliers.