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This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a "variable-preconditioned LMS" calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.

A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them simultaneously in a stepwise feedback loop. The calibration achieves 20 dB spur reduction with little area and power overhead. The chip is implemented in 40 nm CMOS and consumes 46 $\mu \text{W}$ from a 1 V supply, and achieves 64.1 dB SNDR and a FoM of 5.5 fJ/conversion-step at Nyquist.

A 1.3 nJ/b IEEE 802.11ah TX for IoT applications is presented. A fully-digital polar architecture consisting of an all-digital PLL-based frequency modulator and an AM-retiming $\Delta \Sigma $ switched-capacitor PA (SC-PA) achieves more than $10\times $ power reduction than state-of-the-art OFDM TXs. Several circuit-design techniques such as LSB truncation error feedback are proposed to efficiently pre-process the AM/PM data to improve the TX performance. A design approach of the SC-PA for optimum overall efficiency is introduced. The PLL spur level is reduced to 55 dBc by a switched-capacitor based digital-to-time converter. A dynamic divider is implemented together with a 1.8 GHz oscillator for efficient LO generation. Fabricated in a 40 nm CMOS process, this TX fulfills all the IEEE 802.11ah mandatory-mode PHY requirements with 4.4% EVM and > 4.8 dB spectral mask margin, while consuming 7.1 mW from a 1 V supply when delivering 0 dBm output power.

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and $16.7~\mu \text{W}$ at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.

A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187μW and 16.7μW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.

A WiFi (IEEE 802.11g) and BLE combo transmitter (TX) for IoT applications is presented. A wideband digital polar architecture consisting of an all-digital PLL-based frequency modulator and a switched-capacitor digitally-controlled PA achieves optimal energy efficiency for both WiFi and BLE. The dynamic FM correction and AM alias suppression techniques are applied to support 20MHz 802.11g. Implemented in 28nm CMOS technology with 0.9V supply, this highly reconfigurable TX achieves -22dB EVM for 802.11g up to MCS4 and 1.6% FSK error for BLE. The transmitter only occupies 0.65 mm2 and consumes 27mW and 15mW with OdBm output power for WiFi and BLE, respectively. It results in an excellent energy efficiency of 0.62nJ/b. © 2018 IEEE.

This paper presents a digital active electrode (DAE) system for multi-parameter biopotential signal acquisition in portable and wearable devices. It is built around an IC that performs analog signal processing and digitization with the help of on-chip instrumentation amplifiers, a 12 bit ADC and a digital interface. Via a standard ${\rm I}^{{2}}{\rm C}$ bus, up to 16 digital active electrodes (15-channels) can be connected to a commercially available microcontroller, thus significantly reducing system complexity and cost. In addition, the DAE utilizes an innovative functionally DC-coupled amplifier to preserve input DC signal, while still achieving state-of-the-art performance: 60 nV/sqrt(Hz) input-referred noise and ${\pm} $ 350 mV electrode-offset tolerance. A common-mode feedforward scheme improves the CMRR of an AE pair from 40 dB to maximum 102 dB.

This work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and -106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation, a novel digitally time-dithered SCPA ramping technique is proposed. The presented RX and TX consume 8mW and 113mW, respectively, from a supply as low as 1.2V.

The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a significant share of the total energy of these ULP transceivers which are typically powered by small batteries. Therefore, a fractional-N PLL needs to perform LO frequency synthesis and modulation with a very stringent power budget, i.e., below 1mW [1]. A digital PLL is favored in these applications because of the benefit of small area, which is also a critical cost consideration in IoT. On the other hand, the LO quality generated by these ULP PLLs cannot be compromised, and it needs to fulfil the RF requirements defined in the IoT standards, e.g., Bluetooth Low Energy (BLE). Although the integrated phase error is less stringent in IoT standards, the spectral purity requirements remain critical in order to fulfill the regional spectrum regulations, e.g., FCC. A high fractional spur level due to the non-linearity in PLLs (e.g., from a TDC) introduces the unwanted emission. In this work, we present a ULP dividerless digital PLL with a power-efficient spur-mitigation technique. Furthermore, one of the critical issues of the dividerless (or sub-sampling) PLLs, the lack of frequency capture capability without the assistance of an extra power-hungry frequency-locked-loop (FLL), is addressed and mitigated by the proposed digital phase unwrap technique.

Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (XO) generates a stable reference clock for the PLL to synthesize a carrier and to derive clocks for all other parts of the transceiver SoC, e.g., ADC and the digital baseband. The typical start-up time (T s ) of an XO is relatively long (∼ms) due to a high quality factor of the crystal quartz. This leads to a significant (up to 30%) power overhead for a highly duty-cycled transceiver with a short packet format, e.g., the packet length is as short as 128µs in BLE (Fig. 5.3.1). A reduction of T s of the XO is necessary, at the same time, the power overhead to enable a fast start-up should be minimized in order to reduce the overall energy consumption (Fig. 5.3.1).

A 2.4GHz transceiver SoC, operating at minimum 0.9V, is presented as a power-efficient and cost-effective solution for the coming Internet of Things (IoT) platform. The transceiver is compliant with Bluetooth Low Energy (BLE) 4.0/4.2/5.0 PHY and 802.15.4 standards. The measured sensitivity is −93dBm at 1V, and TX output power is 1dBm. Direct battery attachment is feasible, due to the 1.5µW deep-sleep power which enables µW-range average power consumption without Low Drop-Out (LDO) regulator. The radio is fabricated in 40nm CMOS technology.

This paper presents an ultra-low-power (ULP) IEEE 802.11ah fully-digital polar transmitter (TX). IEEE 802.11ah is a new Wi-Fi protocol optimized for Internet-of-Everything (IoE) applications. Compared to other IoE standards like Bluetooth or ZigBee, its sub-GHz carrier frequency and mandatory modes with 1MHz/2MHz channel bandwidths allow devices to operate in a longer range with scalable data-rates from 150kb/s to 2.1Mb/s. Moreover, the use of OFDM improves link robustness against fading, especially in urban environments, and achieves a higher spectral efficiency. The key design challenges of an IEEE 802.11ah TX for IoE applications are to meet the tight spectral mask and error-vector-magnitude (EVM) requirements as for conventional Wi-Fi standards (e.g., 802.11n/g), while achieving low power consumption required by IoE applications. The presented TX applies a fully-digital polar architecture with a 1V supply, and it achieves more than 10× power reduction compared to the state-of-the-art OFDM transceivers [1–4]. Without any complicated PA pre-distortion techniques as in [5], it passes all the PHY requirements of the mandatory modes in IEEE 802.11ah with 4.4% EVM, while consuming 7.1mW with 0dBm output power.

Near/sub-threshold operation is promising to achieve energy minimization when high performance is not required. The device sizing in sub-threshold region is different from super-threshold region due to significantly different IV characteristics and impact of parasitic effects in these two regions. We have investigated the impact of the inverse narrow width effect (INWE) on transistor drain current in the near/sub-threshold region at three different technology nodes (90 nm, 65 nm, and 40 nm) and proposed an INWE-aware sub-threshold device sizing method to mitigate the impact of INWE to reduce delay, power consumption and area. We applied the proposed device sizing method to designing an INWE-aware standard cell library and achieved up to 20% less delay, 34% less power consumption and 47% less area, compared with the sub-threshold library designed using conventional sizing method. For further optimization, we proposed a dual-width library by combining the INWE-aware library and the minimum sized library. A near-threshold baseband processor designed with the dual width library achieved a total power consumption of ~ 4 μW with 6 MHz at 0.5 V, which is 30% better than the counterpart design.

An energy-efficient, flexible radio SoC with RF front-end (RFFE), digital baseband (DBB) and microcontroller (MCU) for medical/healthcare applications in 315/400 MHz bands is presented. The SoC is fully-compliant with the IEEE 802.15.6 standard in 400MHz bands, and also supports proprietary modes, including high data rate (HDR) modes with x2/4/8 data rates (max 3.6Mb/s) to support applications like EEG, and low-power modes with 1/16 data rate to minimize sensor node power consumption. The total power consumption of 3.5mW (RX, 3.6Mb/s, -77dBm sensitivity) enables best-in-class power efficiency of 1nJ/bit.

This paper presents an ultra-low power wireless transceiver specialized for but not limited to medical implantable applications. It operates at the 402-405-MHz medical implant communication service band, and also supports the 420-450-MHz industrial, scientific, and medical band. Being IEEE 802.15.6 standard compliant with additional proprietary modes, this highly configurable transceiver achieves date rates from 11 kb/s to 4.5 Mb/s, which covers the requirements of conventional implantable applications. The phase-locked loop-based transmitter architecture is adopted to support various modulation schemes with limited power budget. The zero-IF receiver has programmable gain and bandwidth to accommodate different operation modes. Fabricated in 40-nm CMOS technology with 1-V supply, this transceiver only consumes 1.78 mW for transmission and 1.49 mW for reception. The ultra-low power consumption together with the 15.6-compliant performance in term of modulation accuracy, sensitivity, and interference robustness make this transceiver competent for various implantable applications.

This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver [1-3] is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mWforRXand4.4mWforTX.

Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.

Dry active electrodes (AE), i.e., the combination of dry electrodes with in situ amplification, are increasingly used for biopotential measurements in emerging healthcare and lifestyle applications [1]. Compared to gel-based wet electrodes, dry electrodes enable fast set-up time, greater user comfort, and long-term monitoring. AE amplifiers ensure local amplification providing improved robustness to noise interference and cable motion artifacts. However, current AEs have analog outputs requiring powerful analog buffers to drive biopotential signals over measurement cables. Furthermore, analog outputs must be digitized by the back-end (BE) system [2,3]. Besides, parameter mismatch between AEs limits the overall CMRR. CMFB [1] or CMFF [2] helps but comes at the expense of increased number cables between the BE and AEs. These problems significantly increase the overall system complexity and cost.

Ultra-low-power (ULP), short-range wireless connectivity is becoming increasingly relevant to a wide range of sensor and actuator node applications, ranging from consumer lifestyle to medical applications. In recent years, a multitude of wireless standards has been proposed to meet differing requirements of individual application domains such as data rates, range, QoS, peak and average power consumption. From a commercial perspective, a single radio component that is capable of supporting multiple wireless standards - targeting multiple application domains/markets - while reducing integration costs is highly preferable. At the same time, the multi-standard support may not compromise low-power operation or silicon area.

A theoretical model for non-coherent start-of-frame-delimiter (SFD) detection in IEEE 802.15.4a is presented and closed form solutions for SFD threshold and signal-to-noise ratio (SNR) estimation are derived. The derived results are implemented in an impulse radio ultra wide band (IR-UWB) demonstrator operating in the 6–10.6 GHz UWB band. The demonstrator is designed for low power operation (in the mW range for combined digital base band (DBB) & radio frequency (RF)). The transmitter (TX) RF is duty cycled at pulse level and the receiver (RX) RF is switched to pulse level duty cycling when possible. Moreover, digital TX and RX resources are only switched on when needed. Measurement results are in close agreement with the derived closed form solutions.

A scalable low power Impulse Radio (IR) receiver baseband has been developed for an around-the-body audio streaming use case, supporting both coherent and non-coherent operation modes. With careful hardware/software co-optimization, the receiver algorithms are implemented using an Application-Specific-Instruction-set-Processor (ASIP) and several optimized hardware accelerators, allowing scalability and support of multi-mode operations in an energy-efficient manner. The receiver baseband is designed in a 90 nm standard CMOS process and is fully verified with the RF frontend. By using an all-digital parallel synchronization module, a short timing acquisition phase is realized, reducing synchronization overhead. In combination with a comprehensive set of low power measures, including hardware/software partitioning, parallelism, module level clock gating, multiple clock domains, operand isolation, multi voltage domains (MVD) and power gating techniques, an average power consumption of 5.6 mW for a 0.85 Mb/sec data rate mode is realized. This corresponds to 10.1pJ/bit for the coherent data processing of an 84 data bytes packet. Furthermore, the design is capable of processing 499.2 MSamples/sec at 840 mV.

Any around-the-body wireless system faces challenging requirements. This is especially true in the case of audio streaming around the head e.g. for wireless audio headsets or hearing-aid devices. The behind-the-ear device typically serves multiple radio links e.g. ear-to-ear, ear-to-pocket (a phone or MP3 player) or even a link between the ear and a remote base station such as a TV. Good audio quality is a prerequisite and mW-range power consumption is compulsory in view of battery size. However, the GHz communication channel typically shows a significant attenuation; for an ear-to-ear link, the attenuation due to the narrowband fade dominates and is in the order of 55 to 65dB [1]. The typically small antennas, close to the human body, add another 10 to 15dB of losses. For the ear-to-pocket and the ear-to-remote link, the losses due to body proximity and antenna size reduce, however the distance increases resulting in a similar link budget requirement of 80dB.

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400 aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90 nm CMOS occupies only 0.11 mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5 GS/s at 0.75 V supply, and 1 GS/s at 1 V supply with 0.47 mW and 1.6 mW power consumption respectively. With an ENOB of 4.7 and 4.8 bits, this leads to energy efficiencies of 36 and 57 fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct modulated transmitter transmits OOK signal with 0 dBm peak power, and it consumes 2.59 mW with 50% OOK. The transmitter front-end supports up to 10 Mbps. The transmitter digital baseband enables digital pulse-shaping to improve spectrum efficiency. The super-regenerative receiver front-end supports up to 5 Mbps with -75dBm sensitivity. Including the digital part, the receiver consumes 715 μW at 1 Mbps data rate, oversampled at 3 MHz. At the system level the transceiver achieves PER=10 -2 at 25 meters line of site with 62.5 kbps data rate and 288 bits packet size. The transceiver is integrated in an electrocardiogram (ECG) necklace to monitor the heart's electrical property.

A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. The complete, duty-cycled transmitter provides +1dBm peak output power, consuming 4.4mW. The receiver front-end shows +88dBm sensitivity at 0.85Mbps and a digital synchronization algorithm enables real-time duty cycling, resulting in a mean power consumption of 3mW. © 2011 IEEE.