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This presentation will examine at a high level the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D) and films metrology, and present the extensive list of applications for which metrology solutions are needed. Progress will be shown in terms of the IEEE-IRDS roadmap. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment.

The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

Low-cost, high-throughput and nondestructive metrology of truly three-dimensional (3-D) targets for process control/monitoring is a critically needed enabling technology for high-volume manufacturing (HVM) of nano/micro technologies in multi-disciplinary areas. In particular, a survey of the typically used metrology tools indicates the lack of a tool that truly satisfies the HVM metrology needs of 3-D targets, such as high aspect ratio (HAR) targets. Using HAR targets here we demonstrate that through-focus scanning optical microscopy (TSOM) is a strong contender to fill the gap for 3-D shape metrology. Differential TSOM (D-TSOM) images are extremely sensitive to small and/or dissimilar types of 3-D shape variations. Based on this here we propose a TSOM method that involves creating a database of cross-sectional profiles of the HAR targets along with their respective D-TSOM signals. Using the database, we present a simple-to-use, low-cost, high-throughput and nondestructive process-monitoring method suitable for HVM of truly 3-D targets, which also does not require optical simulations, making its use straightforward and automatable. Even though HAR targets are used for this demonstration, the similar process can be applied to any truly 3-D targets with dimensions ranging from micro-scale to nano-scale. The TSOM method couples the advantage of analyzing truly isolated targets with the ability to simultaneously analyze many targets present in the large field-of-view of a conventional optical microscope.

Microscopically, a rough edge can be considered as a set of exclusions (i.e., bumps) and inclusions (i.e., divots) along a sidewall. These local perturbations along the sidewall can be thought of as the most basic building blocks of the geometry of rough edges. However, these two structural geometries image differently under critical dimension scanning electron microscopes (CD-SEM), and also when scanned from different directions. An understanding of these imaging differences should be important to improving roughness measurement accuracy. In this work, images from using Monte Carlo and analytical simulations of different sizes of exclusions and inclusions on flat edges are used to better understand the effects of the local microgeometry of the edge, and also how various SEM algorithm choices, parameters, beam size/shape, charging, scan direction, and pixel size/scanning scheme influence SEM line edge uncertainties for such features. Furthermore, how these errors interact with roughness power spectral density (PSD) metrics will be explored, imparting knowledge for optimizing roughness PSD measurement with minimized error.

In the version of this Review Article originally published, the labelling of the reflected beam in Fig. 4a was incorrect. This has now been corrected in the Review Article.

In-line metrologies currently used in the semiconductor industry are being challenged by the aggressive pace of device scaling and the adoption of novel device architectures. Metrology and process control of three-dimensional (3-D) high-aspect-ratio (HAR) features are becoming increasingly important and also challenging. In this paper we present a feasibility study of through-focus scanning optical microscopy (TSOM) for 3-D shape analysis of HAR features. TSOM makes use of 3-D optical data collected using a conventional optical microscope for 3-D shape analysis. Simulation results of trenches and holes down to the 11 nm node are presented. The ability of TSOM to analyze an array of HAR features or a single isolated HAR feature is also presented. This allows for the use of targets with area over 100 times smaller than that of conventional gratings, saving valuable real estate on the wafers. Indications are that the sensitivity of TSOM may match or exceed the International Technology Roadmap for Semiconductors (ITRS) measurement requirements for the next several years. Both simulations and preliminary experimental results are presented. The simplicity, lowcost, high throughput, and nanometer scale 3-D shape sensitivity of TSOM make it an attractive inspection and process monitoring solution for nanomanufacturing.

This paper will provide a high level overview of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D) and films metrology, and present the extensive list of applications for which metrology solutions are needed. Commonalities and differences among the various applications will be shown. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment.

Critical dimension scanning electron microscope (CD-SEM) metrology has long used empirical approaches to determine edge locations. While such solutions are very flexible, physics-based models offer the potential for improved accuracy and precision for specific applications. Here, Monte Carlo simulation is used to generate theoretical linescans from single step and line/space targets in order to build a physics-based analytical model, including the presence of bottom footing and top corner rounding. The resulting analytical linescan model fits the Monte Carlo simulation results for different feature heights, widths, pitches, sidewall angles, bottom footing, and top corner rounding. This model has also been successfully applied to asymetric features such as sidewall spacers encountered in self-aligned double patterning.

Successful in-line metrology is imperative for a fab to achieve profitable production yields. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success and is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of mission-critical production processes. This article gives a high-level overview of the findings of the ISMI metrology program and details some of the major approaching manufacturing challenges.

The conventional premise, long-touted among the semiconductor processing community, that metrology is a ldquonon-value-added necessary evil,rdquo is a misleading and dangerous assertion, which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled ldquovalue-addedrdquo processing steps in lithography and etch, such that they can be considered integral parts of the processes. Various key trends in modern, state-of-the-art processing such as optical proximity correction, design for manufacturability, and advanced process control are based, at their hearts, on the assumption of fine-tuned metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities to create value through the engineering of tight and targetable process distributions. Such distributions make possible predictability in speed-sorts and in other parameters, which results in a high-end product. Additionally, significant reliance has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology team using quality practices. This paper will explore the relationships among present and future trends and challenges in metrology, including equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology will be demonstrated to have shifted to being a ldquokey enabler of large revenues,rdquo debunking the out-of-date premise that metrology is ldquonon-value-added.rdquo

The new device architectures and materials being introduced for sub-10nm manufacturing, combined with the complexity of multiple patterning and the need for improved hotspot detection strategies, have pushed current wafer inspection technologies to their limits. In parallel, gaps in mask inspection capability are growing as new generations of mask technologies are developed to support these sub-10nm wafer manufacturing requirements. In particular, the challenges associated with nanoimprint and extreme ultraviolet (EUV) mask inspection require new strategies that enable fast inspection at high sensitivity. The tradeoffs between sensitivity and throughput for optical and e-beam inspection are well understood. Optical inspection offers the highest throughput and is the current workhorse of the industry for both wafer and mask inspection. E-beam inspection offers the highest sensitivity but has historically lacked the throughput required for widespread adoption in the manufacturing environment. It is unlikely that continued incremental improvements to either technology will meet tomorrow’s requirements, and therefore a new inspection technology approach is required; one that combines the high-throughput performance of optical with the high-sensitivity capabilities of e-beam inspection. To support the industry in meeting these challenges SUNY Poly SEMATECH has evaluated disruptive technologies that can meet the requirements for high volume manufacturing (HVM), for both the wafer fab [1] and the mask shop. Highspeed massively parallel e-beam defect inspection has been identified as the leading candidate for addressing the key gaps limiting today’s patterned defect inspection techniques. As of late 2014 SUNY Poly SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for defect inspection. A champion approach has been identified based on a multibeam technology from Carl Zeiss. This paper includes a discussion on the need for high-speed e-beam inspection and then provides initial imaging results from EUV masks and wafers from 61 and 91 beam demonstration systems. Progress towards high resolution and consistent intentional defect arrays (IDA) is also shown.

New device architectures and materials are being introduced to develop 10 and 7 nm node manufacturing processes. In addition, the increasing complexity of multiple patterning adds significant yield challenges. The critical metrology challenges for yield assurance include defect control, control of critical dimension and critical dimension uniformity, and pattern placement control. To support the industry in meeting those challenges SEMATECH continues to evaluate new disruptive metrology technologies that can meet the requirements for high volume manufacturing (HVM). High-speed massively parallel e-beam defect inspection has the potential to address the key gaps limiting today's patterned defect inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. While SEMATECH targets patterned defect inspection first, the technology also has the potential to support the increasing number of hot spot inspection requirements related to critical dimension uniformity and pattern placement that come with self-aligned quadruple patterning. In addition to wafer applications, next generation mask inspection will benefit from a faster high resolution inspection technology. In late 2014 SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for patterned wafer inspection. The selection of a champion technology was made and a core technology maturation phase started with the goal of enabling the eventual commercialization of an HVM system. This paper begins with a brief overview of the industry need and the program being developed to address it. Key technical topics pertaining to imaging performance and defect sensitivity are then examined. Performance data from early proof of concept systems will be shown. The capabilities in development to accurately access defect sensitivity using the core technology will be discussed, and initial results for two types of samples will be provided. Development towards the next generation of non-proprietary test samples will also be presented.

Electron beam induced surface damage in general, and resist shrinkage in particular, are serious issues in any form of electron beam based metrology. Previous studies investigated dimensional changes that occur in resists that were exposed to electron beams. This work builds on these previous studies to consider changes to the material properties of the exposed resists and other materials using quantitative nano-mechanical mapping scanning probe microscopy. Initial data has shown clearly that there are measurable material differences between pre- and post-electron beam exposure. To study this change iArF photo-resists are exposed to varying electron beam energies and doses. These regions are then measured via SPM for dimensional and material property changes. These changes in the exposed areas are correlated to those predicted by modeled results.

SEMATECH aims to identify and enable disruptive technologies to meet the ever-increasing demands of semiconductor high volume manufacturing (HVM). As such, a program was initiated in 2012 focused on high-speed e-beam defect inspection as a complement, and eventual successor, to bright field optical patterned defect inspection [1]. The primary goal is to enable a new technology to overcome the key gaps that are limiting modern day inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. The program specifically targets revolutionary solutions based on massively parallel e-beam technologies, as opposed to incremental improvements to existing e-beam and optical inspection platforms. Wafer inspection is the primary target, but attention is also being paid to next generation mask inspection. During the first phase of the multi-year program multiple technologies were reviewed, a down-selection was made to the top candidates, and evaluations began on proof of concept systems. A champion technology has been selected and as of late 2014 the program has begun to move into the core technology maturation phase in order to enable eventual commercialization of an HVM system. Performance data from early proof of concept systems will be shown along with roadmaps to achieving HVM performance. SEMATECH’s vision for moving from early-stage development to commercialization will be shown, including plans for development with industry leading technology providers.

SEMATECH has initiated a program to develop massively-parallel electron beam defect inspection (MPEBI). Here we use JMONSEL simulations to generate expected imaging responses of chosen test cases of patterns and defects with ability to vary parameters for beam energy, spot size, pixel size, and/or defect material and form factor. The patterns are representative of the design rules for an aggressively-scaled FinFET-type design. With these simulated images and resulting shot noise, a signal-to-noise framework is developed, which relates to defect detection probabilities. Additionally, with this infrastructure the effect of detection chain noise and frequency dependent system response can be made, allowing for targeting of best recipe parameters for MPEBI validation experiments, ultimately leading to insights into how such parameters will impact MPEBI tool design, including necessary doses for defect detection and estimations of scanning speeds for achieving high throughput for HVM.

Critical dimension scanning electron microscope (CD-SEM) metrology has long used empirical approaches to determine edge locations. While such solutions are very flexible, physics-based models offer the potential for improved accuracy and precision for specific applications. Here, Monte Carlo simulation is used to generate theoretical linescans from single step and line/space targets in order to build a physics-based analytical model. The resulting analytical model fits the Monte Carlo simulation results for different feature heights, widths, and pitches. While more work is required to further develop this scheme, this model is a candidate for a new class of improved edge detection algorithms for CD-SEMs.

A new SEM technology, Advantest's Wafer MVM-SEM E3310, is becoming available that allows quantitative, image-based 3D profile metrology of nanoscale features. CD-AFM is generally employed for 3D profile information, but this technique has its own limitations for 1Xnm node production due to tip size constraints in the tightest spaces, and due to finite tip lifetime which can influence measurement stability. Using the patented multi-channel detector technology, this system can acquire information of surface concave and convex features and relative side wall angle (SWA) and height, quickly and non-destructively for nanoscale structures [1] [2]. Here we evaluate this new technology and demonstrate its applicability to contemporary advanced structures.

Semiconductor devices continue to shrink in size with every generation. These ever smaller structures are challenging the resolution limits of current analytical and inline metrology tools. We will discuss the results of a study of critical dimension small angle x-ray scattering (CDSAXS) comparing the measured intensity from a laboratory source and a synchrotron to determine the improvements in compact x-ray source technology necessary to make CDSAXS a high throughput metrology method. We investigated finFET test structures with and without a high-k gate dielectric coating. The HfO2-based high-k gate dielectric substantially increased the scattering intensity. We found that single-angle laboratory source measurements of 15 min from HfO2-coated finFETs had sufficient scattering intensity to measure the higher order peaks necessary for obtaining high-resolution dimensional fits. Identical bare silicon finFETs required at least 2 h of exposure time for equivalent data quality. Using these structures, we measured the scattering efficiency and determined the required photon flux for next generation x-ray sources to make an inline CDSAXS tool high throughput.

SEMATECH has initiated a program to accelerate the development and commercialization of multi-electron beam based technologies as successor for wafer defect inspection in high volume semiconductor manufacturing. This paper develops the basic electron-optical performance requirements and establishes criteria for tool specifications. The performance variations within a large array of electron beams must be minimal in order to maximize defect capture rates while simultaneously minimizing false counts, so a series of experimental evaluations are described to quantify the random and systematic variations in beam current, spot size, detector channel noise level, and defect sensitivity.

Line-edge roughness (LER) and linewidth roughness (LWR) in lithography are best characterized by the roughness power spectrum density (PSD), or similar measures of roughness frequency and correlation. The PSD is generally thought to be described well by three parameters: standard deviation, correlation length, and roughness exponent. The next step toward enabling these metrics for pertinent industrial use is to understand how real metrology errors interact with these metrics and what should be optimized on the critical dimension scanning electron microscopy (CD-SEM) to improve error budgets. In this work, Java Monte Carlo Simulator of Secondary Electrons (JMONSEL) simulation is used to better understand how various SEM parameters, beam size/shape, and sample profile influence SEM line edge uncertainty and also some of the systematic shifts in edge location assignment. A thorough understanding of the impact of the SEM on the measurement results enables better measurement of LER PSD and better interpretation of measurement results.

This paper will explore the possibilities of critical dimension scanning electron microscope (CD-SEM) metrology at sub- 10 nm feature sizes using modeling. JMONSEL simulations will be used to illustrate SEM waveforms for very small features, as a function of beam energy, feature size, profile height and sidewall angle. It will also be shown that the dimensions of the electron beam and interaction volume have very strong influence on the results. Using modeled results, an assessment on required image quality for future tools will be presented, along with a framework for linking spot size and image resolution. Additionally, from the generated waveforms, various measurement algorithms will be evaluated for such future nanometer-scale applications.

A new SEM technology is becoming available that allows image-based 3D profile metrology of nanoscale features. Using patented multi-channel detector technology, this system can acquire information of surface concave and convex features, and sidewall angle (SWA) and height of profiles, quickly and non-destructively for nanoscale structures such as fin field-effect transistors (FinFETs), using electron beam technology with its well-known long probe lifetime, stability and small probe size. Here we evaluate this new technology and demonstrate its applicability to contemporary advanced structures such as FinFETs, including not only CD, but also profile, SWA, top corner rounding (TCR) and bottom corner rounding (BCR).

One of the major challenges associated with insertion of a directed self-assembly (DSA) patterning process in high volume manufacturing (HVM) is finding a non-destructive, yield-compatible, consistent critical dimension (CD) metrology process. Current CD scanning electron microscopy (CD-SEM) top-down approaches do not give the profile information for DSA patterns, which is paramount in determining the subsequent pattern transfer process (etch, for example). SEMATECH, in cooperation with some of the leaders of the metrology and DSA materials supply chain, has led an effort to address such metrology challenges in DSA. We have developed and evaluated several techniques (including a scatterometry-based method) that are potentially very attractive in determining DSA pattern profiles and have embedded bridging in such patterns without resorting to destructive cross-section imaging. We show how such processes could be fine-tuned to enable their insertion for DSA pattern characterization in an HVM environment.

In-line metrologies currently used in the semiconductor industry are being challenged by the aggressive pace of device scaling and the adoption of novel device architectures. In defect inspection, conventional bright field techniques will not likely be able to meet defect capture rate requirements beyond the 16 nm node. Electron beam-based inspection is able to meet resolution limits well below this node, but operates at a significantly lower throughput. It, therefore, has become necessary to explore alternative approaches with the potential to meet both resolution and throughput requirements. Critical dimension (CD) metrology, on the other hand, is less challenged by resolution than by the increasingly 3D nature of the information that needs to be collected from modern device structures. It is therefore valuable to explore metrology techniques that are sensitive to spatial variations across the entire volume of the interrogated feature. Through-focus scanning optical microscopy (TSOM) is a novel method that allows conventional optical microscopes to collect dimensional information down to the nanometer level by combining 2D optical images captured at several through-focus positions. This relatively simple technique is inexpensive and has high throughput, making it attractive for a variety of semiconductor metrology applications, such as CD, photomask, overlay, and defect metrologies. In this work, we expand on the analysis of TSOM as a potential technique for defect inspection and study its ability to characterize 3D high aspect ratio (HAR) features. For defect inspection applications, we extend the simulation space well beyond the 11 nm node, based on dense features with CDs ranging from 13 nm to 7 nm. The optical response of a variety of patterned defect modes, sizes, and heights was likewise explored under different polarization and wavelength illumination conditions. Results indicate TSOM has the ability to extract defect signal for most of the cases studied. Work on HAR features focused on exploring 3D sensitivity to features such as bottom CD, sidewall angle, and depth. HAR targets were studied using simulations down to the 11 nm node. Promising results were observed in terms of sensitivity to bottom CD, sidewall angle, and depth.

Photoresist shrinkage (i.e., line slimming) is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features [1] [2] [3] [4] [5]. It influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. This error source will be a factor in CD-SEM metrology on polymer materials in EUV lithography. Recent work has demonstrated improved understanding of the trends in the shrinkage response depending on electron beam and target parameters in static measurements [2] [3] [4] [5] [6]. Some research has highlighted a second mode of shrinkage that is apparent over time and progresses as a function of time between consecutive measurements, a form of “dynamic shrinkage” that appears to be activated by electron beam, in which the activated feature perpetually and logarithmically shrinks [7] [8]. Another work has demonstrated that as pitches continue to get smaller with resulting reductions in spaces between lines, charging may emerge as an additional, competing, unpredictable error source for CD-SEM metrology on dense photoresist features, an issue that is predicted to become more common as these spaces become more confined [9]. In this work, we explore the static shrinkage behaviors of various EUV photoresists into the 16 nm half-pitch node, with samples generated using the advanced EUV lithography capable of generating such tight pitches [10]. Dynamic shrinkage behavior was explored on these materials last year [15]. The static shrinkage behaviors will be validated to show compliance with the SEMATECH shrinkage model [5] [6] on small EUV resist features. Using the results of the model fits, a simulation study will predict the shrinkage trends at future nodes. Further studies will confirm whether or not charging phenomena are observable, and the beginning of a charging simulation study will be discussed.

We have demonstrated that transmission critical dimension small angle X-ray scattering (CD-SAXS) provides high accuracy and precision CD measurements on advanced 3D microelectronic architectures. The competitive advantage of CD-SAXS over current 3D metrology methods such as optical scatterometry is that CD-SAXS is able to decouple and fit cross-section parameters without any significant parameter cross-correlations. As the industry aggressively scales beyond the 22 nm node, CD-SAXS can be used to quantitatively measure nanoscale deviations in the average crosssections of FinFETs and high-aspect ratio (HAR) memory devices. Fitting the average cross-section of 18:1 isolated HAR contact holes with an effective trapezoid model yielded an average pitch of 796.9 ± 0.4 nm, top diameter of 70.3 ± 0.9 nm, height of 1088 ± 4 nm, and sidewall angle below 0.1°. Simulations of dense 40:1 HAR contact holes and FinFET fin-gate crossbar structures have been analyzed using CD-SAXS to inquire the theoretical precision of the technique to measure important process parameters such as fin CD, height, and sidewall angle; BOX etch recess, thickness of hafnium oxide and titanium nitride layers; gate CD, height, and sidewall angle; and hafnium oxide and titanium nitride etch recess. The simulations of HAR and FinFET structures mimic the characteristics of experimental data collected at a synchrotron x-ray source. Using the CD-SAXS simulator, we estimate the measurement capabilities for smaller similar structures expected at future nodes to predict the applicability of this technique to fulfill important CD metrology needs.

Metrology measurement and defect inspection steps in routes are more pervasive than many people realize and the number continues to grow. Digging deeper, it turns out that E-beam metrology and defect inspection tools typically occupy the most overall steps and therefore are extremely critical tools for semiconductor development and manufacturing. The Critical Dimension Scanning Electron Microscope (CDSEM) is an E-beam tool responsible for image-based structural metrology measurements while the E-beam review (EBR) and E-beam inspection (EBI) tools are responsible for defect inspection. The CDSEM faces significant future challenges in a world where device architectures are changing (as with the FinFET device), increasing the need for more structural measurement parameters such as sidewall angle, height and undercut, than the CDSEM can deliver. These applications are now migrating to scattering-based tools, also referred to as model- or computational-based structural metrology techniques. We explore the history of the CDSEM, the key fundamental limits (primarily resolution) of the CDSEM preventing it from capturing these applications and assess if an image-based structural metrology tool is still needed given the niche that scattering tools are filling. The answer is yes. Next we discuss whether the CDSEM will eventually meet those needs or if other alternative solutions are needed. Lastly, we discuss an industry survey on which image-based technique holds the most promise to solve these challenges. Regarding defect inspection, resolution is also a concern for the applications that need to detect extremely small defects which current optical-based Brightfield tools cannot address. While resolution is a primary concern in structural metrology, current EBI and EBR tools possess the resolution needed for defect inspection and have extendibility through at least the next advanced technology node. We also explore the niche E-beam is filling in defect inspection, evaluate the idea that a better synergistic solution exists today between the CDSEM and the EBI tools and propose a future E-beam landscape where E-beam tool variety in future fabs is significantly reduced to enhance productivity.

This paper will examine the future for critical dimension (CD) metrology. First, we will present the extensive list of applications for which CD metrology solutions are needed, showing commonalities and differences among the various applications. We will then report on the expected technical limits of the metrology solutions currently being investigated by SEMATECH and others in the industry to address the metrology challenges of future nodes, including conventional CD scanning electron microscopy (CD-SEM) and optical critical dimension (OCD) metrology and new potential solutions such as He-ion microscopy (HeIM, sometimes elsewhere referred to as HIM), CD atomic force microscopy (CD-AFM), CD small-angle x-ray scattering (CD-SAXS), high-voltage scanning electron microscopy (HV-SEM), and other types. A technical gap analysis matrix will then be demonstrated, showing the current state of understanding of the future of the CD metrology space.

One of the key challenges in critical dimension (CD) metrology is finding suitable dimensional calibration standards. The transmission electron microscope (TEM), which produces lattice-resolved images having scale traceability to the SI (International System of Units) definition of length through an atomic lattice constant, has gained wide usage in different areas of CD calibration. One such area is critical dimension atomic force microscope (CD-AFM) tip width calibration. To properly calibrate CD-AFM tip widths, errors in the calibration process must be quantified. Although the use of TEM for CD-AFM tip width calibration has been around for about a decade, there is still confusion on what should be considered in the uncertainty analysis. We characterized CD-AFM tip-width samples using high-resolution TEM and high angle annular dark field scanning TEM and two CD-AFMs that are implemented as reference measurement systems. The results are used to outline how to develop a rigorous uncertainty estimate for TEM/CD-AFM calibration, and to compare how information from the two electron microscopy modes are applied to practical CD-AFM measurements. The results also represent a separate validation of previous TEM/CD-AFM calibration. Excellent agreement was observed.

The focused ion beam (FIB) milling tool is an important component of reference metrology and process characterization, both as a supporting instrument for bulk sample preparation before forwarding to the transmission electron microscope (TEM) and other instruments and as an in situ measurement instrument using angled scanning electron microscopy. As features grow denser, deeper and more demanding, full-profile reference metrology is needed, and this methodology will only grow in importance. Thus, the ability to extract accurate dimensional and profile information out of the crosssectional faces produced by FIB milling is critical. For features that demonstrate perfect symmetry in the plane of the cross section, analyzing images and extracting metrology data are straightforward. However, for industrial materials, symmetry is not a safe assumption: as features shrink, the line edge and sidewall roughness increases as a percentage of the overall feature dimension. Furthermore, with the introduction of more complex architectures such as 3D memory and FinFETs, the areas of greatest interest, such as the intersections of wrap-around gates, cannot be assumed to be symmetrical in any given plane if cut placement is not precisely controlled. Therefore it is important to establish the exact location and repeatability of the cross-section plane, both in terms of coordinate placement and effective angle of the milled surface. To this end, we prepared designed-in line edge roughness samples in the Albany Nanotech facility using SEMATECH's AMAG6 metrology reticle. The samples were thoroughly characterized before being milled by a non-destructive, sidewall-scanning atomic force microscope (AFM). These samples are then milled and measured under varying process and setup parameters using a single-beam FIB with angled SEM. We established methodologies that allow precise alignment of the cut planes of slice-and-view FIB milling to 3D-AFM scan lines to compare repeated sections throughout a feature. This gives us a large amount of data to test the accuracy and repeatability of cut placement using various alignment and recipe setup schemes.

In-line, non-destructive process control metrology of high aspect ratio (HAR) holes and trenches has long been a known gap in metrology. Imaging the bottoms of at-node size contact holes in oxide with aspect rations beyond 10:1 has not yet been demonstrated. Nevertheless, holes and trenches of 30:1, 40:1, or even 60:1 will soon enter production, with these etches being applied to various homogeneous and multi-layer stacks of Si and SiO2. The need comes from Moore's Law and increasing functional density on microchips, on which true 3D memory devices will soon be manufactured. These can take many different forms, but a common building block will be these ultra-HAR etched features. In this work, we show experimental results and simulations from the NIST JMONSEL program to assess the feasibility of measuring such features using both conventional low voltage scanning electron microscopy (SEM) and higher beam energies and low vacuum conditions to ameliorate charging. In our measurements, higher voltage SEM did not improve upon conventional critical dimension (CD)-SEM. Simulations suggest the reason is a failure to overcome a negative oxide potential. Although a signal can in principle be detected from the bottom of contact holes in typical imaging conditions in the CD-SEM, it is likely that it will be very small and possibly below the noise floor.

Through-focus scanning optical microscopy (TSOM) is a novel method [1-8] that allows conventional optical microscopes to collect dimensional information down to the nanometer level by combining 2D optical images captured at several through-focus positions, transforming conventional optical microscopes into truly 3D metrology tools for nanoscale to microscale dimensional analysis with nanometer scale sensitivity. Although not a resolution enhancement method, it has been shown to provide lateral and vertical measurement sensitivity of less than a nanometer [5], comparable to the dimensional measurement sensitivity of other critical dimension (CD) metrology tools. The technique is capable of measuring features far beyond the theoretical resolution limits of optical microscopy, because it can capture much richer data at many z-heights (i.e., through focus). Additionally, TSOM appears to decouple the measurement of profile dimensional changes at the nanoscale, such as small perturbations in sidewall angle and height, with little or no ambiguity, and may be able to analyze target dimensions ranging from as small as 10 nm up to many microns with similar nanometer-scale sensitivity. Furthermore, previous simulation and experimental work has shown this method to be applicable to a variety of target materials and structures, such as nanoparticles, semiconductor memory features, and buried structures under transparent films. Additionally, this relatively simple technique is inexpensive and has high throughput, making it attractive for a variety of semiconductor metrology applications, such as CD, photomask, overlay, and defect metrologies [8]. In-line defect metrology is continuously challenged by the aggressive pace of device scaling. It is expected that the conventional brightfield techniques currently used in semiconductor manufacturing will not be able to meet defect inspection requirements near the 11 nm node. Electron beam-based inspection is able to meet resolution limits well below the 11 nm node, but operates at a significantly lower throughput. It has therefore become necessary to explore alternative approaches that have the potential to meet both resolution and throughput requirements. This work will present TSOM results of simulations and supporting experiments to demonstrate the metrology application of TSOM to features at the ITRS 22 nm node [9], including measurement of linewidths down to 10 nm, showing the ability to measure changes in line height, sidewall angle, and pitch variations. By extension, these results will show the feasibility of applying TSOM to important contemporary metrology problems in measuring doublepatterned features and FinFETs. Additionally, we will theoretically explore the use of TSOM to inspect defects on gatelevel arrays with different CDs down to 15 nm. This theoretical work consisted of modeling the optical response of cross-sectional perturbations and several patterned defect types and sizes using illumination wavelengths ranging from visible to deep ultraviolet (DUV) under different illumination polarizations. The results indicate that TSOM may be able to detect small CD and profile changes in fins of FinFET structures as well as defects that currently challenge conventional brightfield optical methods. The simulation results also indicate an added advantage of the TSOM method to differentiate certain types of defects and their orientations by exhibiting different optical intensity patterns. These results will provide insight into the feasibility of TSOM for CD and yield enhancement metrology.

Photoresist shrinkage (a.k.a. line slimming) is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features [1][2][3][4][5]. In terms of metrology gauge metrics, it influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. This error source will furthermore be a factor in CDSEM metrology on such polymer materials into the era of EUV lithography, such that learning to work around this issue will continue to be necessary. Recent work has demonstrated improved understanding of the trends in the shrinkage response depending on electron beam and target parameters in the static measurement case [2][3][4][5][6]. Another recent work has highlighted a second mode of shrinkage that is apparent over time and progresses as a function of time between consecutive measurements, a form of "dynamic shrinkage" that appears to be activated by electron beam, in which the activated feature perpetually and logarithmically shrinks [7][8]. In this work, we will explore both the static and dynamic shrinkage behaviors of various EUV photoresists. The static shrinkage behaviors will be tested for compliance with the SEMATECH shrinkage model [5][6], and further studies will confirm whether or not the dynamic effects are observable. Knowledge of secondary trends in dynamic shrinkage will also be further explored, including how these vary with electron beam energy, activation dose, feature size, and other parameters.

In this paper, we explore the sensitivity of three-dimensional atomic force microscopy to incremental variation in the sidewall angle of near-vertical features. Measurement results are presented from a specially constructed wafer with continuous variation in sidewall slope across a range of angles just above and below vertical. This sample was scanned with a variety of both tip shapes and sizes using two different scan modes. From the results, we are able to derive cutoff limits for measuring near-vertical angles using aggressive scanning modes and the relative biases of different modes and tips in measuring a range of sidewall angles. This provides information about the measurement limitations of differing instrument configurations, each configuration consisting of a combination of tip and scan mode and sensitivity demarcated in terms of the ability to detect changes in the slope and relative accuracy of the measurement.

Photoresist shrinkage is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features. In terms of metrology gauge metrics, it influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. Because this error source will furthermore be a factor in CD-SEM metrology on polymer materials, learning to work around this issue is necessary. Tool-to-tool matching is another important component of measurement uncertainty that metrologists must control in high volume manufacturing, and photoresist samples are a most difficult case due to shrinkage effects, as tool-to-tool biases can vary based on the sample or other parameters. In this work, we explore different shrinkage effects and their influence on matching. This will include an investigation of how the photoresist shrinkage rate varies with time from the chemical development of the photoresists, which necessitates that measurements on different tools within a group be performed in rapid succession to avoid additional error. The differences in shrinkage rates between static and dynamic load/unload cases will also be addressed, as these effects also influence matching. The results of these dynamic effect experiments will be shown to have far-reaching implications for the shrinkage phenomenon in general. Finally, various sampling schemes for matching will be explored, through both simulation and experiment, for use with shrinking materials. Included is a method whereby various fleet tools measure different locations, once per tool, within a uniform line/space grating. Finally, we will assess how well matching can be achieved using these techniques.

Through-focus scanning optical microscopy (TSOM) is a new metrology method that achieves 3D nanoscale measurement sensitivity using conventional optical microscopes; measurement sensitivities are comparable to what is typical when using scatterometry, scanning electron microscopy (SEM), and atomic force microscopy (AFM). TSOM can be used in both reflection and transmission modes and is applicable to a variety of target materials and shapes. Nanometrology applications that have been demonstrated by experiments or simulations include defect analysis, inspection and process control; critical dimension, photomask, overlay, nanoparticle, thin film, and 3D interconnect metrologies; line-edge roughness measurements; and nanoscale movements of parts in MEMS/NEMS. Industries that could benefit include semiconductor, data storage, photonics, biotechnology, and nanomanufacturing. TSOM is relatively simple and inexpensive, has a high throughput, and provides nanoscale sensitivity for 3D measurements with potentially significant savings and yield improvements in manufacturing.

The aggressive device scaling imposed by the International Technology Roadmap for Semiconductors (ITRS) is introducing additional and more demanding challenges to current in-line monitoring tools. In this paper we present a new probe microscopy based technology, the Rapid Probe Microscope (RPM), which produces nano-scale images using a height contrast mechanism in a non-vacuum environment. The system offers the possibility to address metrology challenges in alternative ways to existing review and inspection tools. This paper presents applications of the RPM process which cater to the requirements of the semiconductor industry. Results on several standard semiconductor wafer layers have been used to demonstrate the capabilities of the RPM process, including nano-scale surface imaging at high image capture rates.

Moore's Law continues to drive improvements to lithographic resolution to increase integrated circuit transistor density, improve performance, and reduce cost. For the 22 nm node and beyond, extreme ultraviolet lithography (EUVL) is a promising technology with λ=13.5 nm, a larger k1 value and lower cost of ownership than other available technologies. For small feature sizes, process control will be increasingly challenging, as small features will create measurement uncertainties, yet with tighter specifications. Optical scatterometry is a primary candidate metrology for EUV lithography process control. Using simulation and experimental data, this work will explore scatterometry's application to a typical lithography process being used for EUV development, which should be representative of lithography processes that will be utilized for EUV High Volume manufacturing (HVM). EUV lithography will be performed using much thinner photoresist thicknesses than were used at the 248nm or 193nm lithography generations, and will probably include underlayers for adhesion improvement; these new processes conditions were investigated in this metrological study.

For many years, lithographic resolution has been the main obstacle in allowing the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. These smaller feature sizes will also require the use of thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in SEMATECH's CD-SEM Unified Specification . In other associated works, we first developed a 1-D model for resist shrinkage for the bottom linewidth and then a 2-D profile model that accounted for shrinkage of all aspects of a trapezoidal profile along a given linescan. A fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized and shaped features. In the 1-D case, calibration of the parameters to describe the photoresist material and the electron beam was all that was required to fit the models to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. The later 2-D model included improvements for solving the CD shrinkage in thin photoresists, which is now of great interest for upcoming realistic lithographic processing to explore the change in resist profile with electron dose and to predict the influence of initial resist profile on shrinkage characteristics. The 2-D model also included shrinkage due to both the primary electron beam directly impacting the profile and backscattered electrons from the electron beam impacting the surrounding substrate. This dose from backscattering was shown to be an important component in the resist shrinkage process, such that at lower beam energies, it dominates linewidth shrinkage. In this work, results from a previous paper will be further explored with numerically simulated results and compared to experimental results to validate the model. With these findings, we can demonstrate the state of readiness of these models for predicting the shrinkage characteristics of photoresist measurements and estimating the errors in calculating the original CD from the shrinkage trend.

NIST has introduced a new standard for dimensional metrology and the calibration of the scanning electron microscope (SEM) scale identifi ed as Reference Material (RM) 8820. RM 8820 was primarily intended to be used for calibrating the X and Y scale (or magnifi cation) in SEMs but, can be used for an many other purposes. Essentially, all laboratory microscopes can be calibrated to this same artifact. The NIST pattern is only one part of a very large array of test structures that were designed for various dimensional metrology purposes useful to semiconductor production technologies. These and other purposes, discussed in the presentation, RM 8820 can also be used on/in any other type of microscope, such as optical and scanning probe microscopes and for scatterometry measurements.

Reference Material 8820 (RM 8820) is a new scanning electron microscope calibration reference material for nanotechnology and nanomanufacturingtion recently released by NIST. This standard was developed to be used primarily for X and Y scale (or magnifi cation) calibrations of scanning electron microscopes from less than 10 times magnifi cation to more than 300 000 times magnifi cation, i.e., from about 10 mm to smaller than 300 nm range instrument fi eld of view (FOV). This standard is identifi ed as RM 8820. This is a very versatile standard, and it can also be used for calibration and testing of other type of microscopes, such as optical and scanning probe microscopes. Beyond scale calibration, RM 8820 can be used for a number of other applications, some of which will be described in this publication.

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. Also, such smaller feature sizes will require thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMI's CD-SEM Unified Specification. A model for resist shrinkage, while derived elsewhere, was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) before e-beam exposure. With these parameters and exhaustive measurements, a fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized features. This work was extended in yet another paper in which we presented a 1-D model for resist shrinkage that can be used to curve-fit to shrinkage curves. Calibration of parameters to describe the photoresist material and the electron beam were all that were required to fit the model to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. In this paper, we extend this work yet again to a 2-D model of a trapezoidal photoresist profile. This model thus allows CD shrinkage in thin photoresist to be solved, which is now of great interest for upcoming realistic lithographic processing. It also allows us to predict the change in resist profile with electron dose and the influence of initial resist profile on shrinkage characteristics. In this work, the results from the previous paper will be shown to be consistent with numerically simulated results, thus lending credibility to these papers' postulations. Also, results from this 2-D profile model can also give clues as to how we might, in the future, model the shrinkage of contour edges of 3-D shapes. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of future photoresist measurement, as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, and even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions and pitches continue to shrink, double patterning (DP) has become more common. Thus automatic recipe setup has needed to incorporate capabilities to deal simultaneously with two layers. This has the benefit of allowing the user to measure the two different CD populations and the image shift in the lithography (i.e., the overlay). Thus automatic recipe creation can be used to characterize the DP pattern for both CD and overlay. DesignGauge, the automatic recipe utility for Hitachi CG series CD-SEMs, is not only capable of offline recipe creation, but also can also directly transfer design-based recipes into standard CD-SEM recipes for use with DP processes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which improves production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, engineering time to generate recipes, and CD-SEM utilization. Another benefit of the application is that recipes are more robust than with conventional direct image-based pattern recognition. This paper explores the feasibility of matching a two-layer GDS pattern to features in an image, allowing for the more complex measurements involved in DP characterization. This work will evaluate DesignGauge with double litho double etch (DLDE DP), including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of the recipe creation, recipe execution, and verification of proper measurements of the dual CD populations and overlay.

A new multipurpose instrument calibration standard has been released by NIST. This standard was developed to be used primarily for X and Y scale (or magnification) calibrations of scanning electron microscopes from less than 10 times magnification to more than 300 000 times magnifi cation, i.e., from about 10 mm to smaller than 300 nm range instrument field of view (FOV). This standard is identifi ed as RM 8820. This is a very versatile standard, and it can also be used for calibration and testing of other type of microscopes, such as optical and scanning probe microscopes. Beyond scale calibration, RM 8820 can be used for a number of other applications, some of which will be described in this publication.

As CMOS transistor critical dimensions (CDs) shrink to 35 nm and below, monitoring and control of line width roughness (LWR) and line edge roughness (LER) will become increasingly important. We used dark-field twodimensional beam profile reflectometry at 405 nm wavelength with a 0.9 numerical aperture (NA) objective to measure the low levels of diffuse scattered light from the roughness on the surfaces of lines in test structures on a wafer created by ISMI. This wafer contains a variety of amorphous etched gate test structures with a range of CDs from approximately 20 nm to 50 nm. Selected structures were thoroughly characterized for CD, LER and LWR by a critical-dimension scanning electron microscope (CD-SEM). The integrated diffuse scattered intensities obtained from structures with different CD and LWR values were compared to LWR as measured by the CD-SEM. The diffuse scattered optical signal intensity showed, at best, a weak correlation to the CD-SEM measured LWR. However a plot of the diffuse scattered intensity versus CD-SEM measured CD showed a strong, but nonlinear, correlation. This indicates that the scattering depends not only on the surface roughness but also on the CD of the line (and presumably other details of the profile).