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We demonstrate a 36$\times$36 gate electrode crossbar that supports 648 narrow-channel field effect transistors (FET) for gate-defined quantum dots, with a quadratic increase in quantum dot count upon a linear increase in control lines. The crossbar is fabricated on an industrial $^{28}$Si-MOS stack and shows 100% FET yield at cryogenic temperature. We observe a decreasing threshold voltage for wider channel devices and obtain a normal distribution of pinch-off voltages for nominally identical tunnel barriers probed over 1296 gate crossings. Macroscopically across the crossbar, we measure an average pinch-off of 1.17~V with a standard deviation of 46.8 mV, while local differences within each unit cell indicate a standard deviation of 23.1~mV. These disorder potential landscape variations translate to 1.2 and 0.6 times the measured quantum dot charging energy, respectively. Such metrics provide means for material and device optimization and serve as guidelines in the design of large-scale architectures for fault-tolerant semiconductor-based quantum computing.

We determine the energy splitting of the conduction-band valleys in two-dimensional electrons confined to low-disorder Si quantum wells. We probe the valley splitting dependence on both perpendicular magnetic field $B$ and Hall density by performing activation energy measurements in the quantum Hall regime over a large range of filling factors. The mobility gap of the valley-split levels increases linearly with $B$ and is strikingly independent of Hall density. The data are consistent with a transport model in which valley splitting depends on the incremental changes in density $eB/h$ across quantum Hall edge strips, rather than the bulk density. Based on these results, we estimate that the valley splitting increases with density at a rate of 116 $\mu$eV/10$^{11}$cm$^{-2}$, consistent with theoretical predictions for near-perfect quantum well top interfaces.

Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high-fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throughput and cryogenic characterization to develop quantum processors. Here we multiplex quantum transport of two-dimensional electron gases at sub-kelvin temperatures. We use commercial off-the-shelf CMOS multiplexers to achieve an order of magnitude increase in the number of wires. Exploiting this technology we advance 300 mm epitaxial wafers manufactured in an industrial CMOS fab to a record electron mobility of (3.9$\pm$0.6)$\times$10$^5$ cm$^2$\slash Vs and percolation density of (6.9$\pm$0.4)$\times$10$^{10}$ cm$^{-2}$, representing a key step toward large silicon qubit arrays. We envision that the demonstration will inspire the development of cryogenic electronics for quantum information and because of the simplicity of assembly, low-cost, yet versatility, we foresee widespread use of similar cryo-CMOS circuits for high-throughput quantum measurements and control of quantum engineered systems.

We investigate the effect of the valley degree of freedom on Pauli-spin blockade readout of spin qubits in silicon. The valley splitting energy sets the singlet-triplet splitting and thereby constrains the detuning range. The valley phase difference controls the relative strength of the intra- and inter-valley tunnel couplings, which, in the proposed Pauli-spin blockade readout scheme, couple singlets and polarized triplets, respectively. We find that high-fidelity readout is possible for a wide range of phase differences, while taking into account experimentally observed valley splittings and tunnel couplings. We also show that the control of the valley splitting together with the optimization of the readout detuning can compensate the effect of the valley phase difference. To increase the measurement fidelity and extend the relaxation time we propose a latching protocol that requires a triple quantum dot and exploits weak long-range tunnel coupling. These opportunities are promising for scaling spin qubit systems and improving qubit readout fidelity, Comment: 8 pages, 6 figures