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A simple yet accurate delay model based on the method of logical effort is presented for the analysis of high-speed current-mode logic (CML) circuits. The model describes the logical effort of a CML gate in terms of its operating current density normalised to the characteristic current density that yields peak transistor cutoff frequency (fT). Since the latter remains largely invariant over technology nodes as a result of constant-field scaling, the proposed logical effort model quantifies the effect of gate sizing, biasing and loading to simplify delay analysis for CML gates. [ABSTRACT FROM AUTHOR]

The effect of process induced variability in long global on-chip interconnects caused by critical dimension control and intrinsic fluctuation of transistor threshold voltage is analysed for current and voltage mode signalling. Projections in scaled CMOS technologies show that current sensing interconnects exhibit smaller mean delay and sensitivity to parameter fluctuations. The standard deviation of delay exhibits an increasing dependency on process variations at the low and high extremes of receiver to driver circuit resistance ratios. An experimental on-chip bus demonstrates the reduced delay variability in current sensing schemes. [ABSTRACT FROM AUTHOR]

An electrically small zigzag dipole antenna patterned directly onto the outer surface of a standard sized circular gelatin capsule using screen printed silver colloidal inks is experimentally evaluated for wireless medication compliance applications. The antenna performance inside the human stomach is analysed using the finite difference time domain method. The radiated field intensity over several US Federal Communications Commission (FCC) telemetry bands shows peak transmission near the skin in the anterior location to the left of the stomach and is most efficient in the 915 MHz band. [ABSTRACT FROM AUTHOR]

Presented is a study of the optimal injection frequency using a time-domain model as a technique to improve the noise suppression in injection-locked ring oscillators. It is found that offsetting the injection signal frequency by roughly half of the one-sided lock range relative to the free-running oscillator frequency can lead to higher noise-suppression bandwidth and lower phase noise. Applied to a five-stage ring oscillator, the model shows good agreement with simulations, which indicate that the optimal injection frequency increases the noise-suppression bandwidth by up to 5×, and lowers the phase noise by 15 dB. [ABSTRACT FROM AUTHOR]