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In this letter, we investigated the threshold voltage VTH stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-todrain voltage (VGD), the VTH shift shows an obvious dependence on the negative gate bias. With a VGS of 0 V, the VTH shift is small and recoverable, while the VTH shifts are substantially larger with more negative gate bias (VGS = -20 V). This larger VTH shifts caused by the negative VGS can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable VTH.

Under reverse-bias stress (i.e., OFF-state stress with V-GS < V-TH) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage (V-TH) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiNx) gate dielectric, as SiNx does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts.

With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with VDS = 0 V and a negative VGS = -30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with VGS < VTH and large VDS) stress, larger negative gate-bias is found to accelerate positive shift in VTH, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when VGS is limited to a few volts below VTH.

Under reverse-bias stress (i.e., OFF-state stress with V-GS < V-TH) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage (V-TH) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiNx) gate dielectric, as SiNx does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts.

In this letter, we investigated the threshold voltage VTH stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-todrain voltage (VGD), the VTH shift shows an obvious dependence on the negative gate bias. With a VGS of 0 V, the VTH shift is small and recoverable, while the VTH shifts are substantially larger with more negative gate bias (VGS = -20 V). This larger VTH shifts caused by the negative VGS can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable VTH.

With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with VDS = 0 V and a negative VGS = -30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with VGS < VTH and large VDS) stress, larger negative gate-bias is found to accelerate positive shift in VTH, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when VGS is limited to a few volts below VTH.

In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting the etched GaN surface from degradation during high-temperature (i.e. at ~ 780°C) process, which is essential for fabricating enhancement-mode GaN MIS-FETs with highly reliable LPCVD-SiNx gate dielectric and fully recessed gate structure. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a Vth of 1.15 V, small on resistance, thermally stable Vth and low positive-bias temperature instability (PBIT).

Ultra-thin-barrier (UTB) AlGaN/GaN heterostructure is utilized for fabrication of normally-OFF GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). The sheet resistance of 2-D electron gas in the UTB Al0.22Ga0.78N(5-nm)/GaN heterostructure is effectively reduced by SiNx passivation grown by low-pressure chemical vapor deposition, from 2570 to 334 Ω/□. The fabricated Al2O3/AlGaN/GaN MIS-HEMTs exhibit normally-OFF behavior with good VTH uniformity and low VTH-hysteresis. 20 mm-gate-width power devices featuring a low Ron of 0.75 Ω (ID,MAX = 6.5 A) are also demonstrated on the platform. © 2016 IEEE.