34 results on '"Bao, Meng-tian"'
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2. TCAD evaluation of single-event burnout hardening design for SiC Schottky diodes
3. Study of TID radiation effects on the breakdown voltage of buried P-pillar SOI LDMOSFETs with P-top region
4. Single-event burnout hardening of RC-IGBT with the raised N-buffer layer
5. Analysis of radiation effect of a novel SOI-Like LDMOS structure
6. Research of single-event burnout and hardened GaN MISFET with embedded PN junction
7. Super junction LDMOS with P-trench and stepped buried oxide layer for high performance
8. Simulation study of single event effects in the SiC LDMOS with a step compound drift region
9. A SiC LDMOS with electric field modulation by a step compound drift region
10. A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer
11. An improved SOI LDMOS with buried field plate
12. Improving breakdown voltage and self-heating effect for SiC LDMOS with double L-shaped buried oxide layers
13. High performance of Trigate Junctionless nanowire MOSFET with P+ Sidewall
14. Novel Layout Design of 4H-SiC Merged PiN Schottky Diodes Leading to Improved Surge Robustness
15. Research of Single-Event Burnout in 1.2-kV Rated CoolSiC Trench MOSFET
16. Performance Evaluation of W-C Alloy Schottky Contact for 4H-SiC Diodes
17. Simulation Study of Single-Event Burnout Reliability for 1.7-kV 4H-SiC VDMOSFET
18. Simulation Study of Single-Event Effects for the 4H-SiC VDMOSFET With Ultralow On-Resistance
19. Impact of Heavy-Ion Irradiation in an 80-V Radiation-Hardened Split-Gate Trench Power UMOSFET
20. Low Switching Loss Split-Gate 4H-SiC MOSFET With Integrated Heterojunction Diode
21. Simulation Study on Single-Event Burnout in Rated 1.2-kV 4H-SiC Super-Junction VDMOS
22. Study of TID Radiation Effects on the Breakdown Voltage of Buried P-Pillar SOI LDMOSFETs
23. Simulation Study of Single-Event Burnout in 1.5-kV 4H-SiC JTE Termination
24. A Snapback Suppressed RC-IGBT With N-Si/n-Ge Heterojunction at Low Temperature
25. Single-Event Burnout Hardening Method and Evaluation in SiC Power MOSFET Devices
26. An Improved V CE–E OFF Tradeoff and Snapback-Free RC-IGBT With P⁺ Pillars
27. TCAD simulation of a breakdown-enhanced double channel GaN metal–insulator–semiconductor field-effect transistor with a P-buried layer
28. Single-Event Burnout Hardness for the 4H-SiC Trench-Gate MOSFETs Based on the Multi-Island Buffer Layer
29. Improving breakdown performance for SOI LDMOS with sidewall field plate
30. Technology Computer Aided Design Study of GaN MISFET With Double P-Buried Layers
31. An Improved 4H-SiC Trench MOS Barrier Schottky Diode With Lower On-Resistance
32. An Improved VCE–EOFF Tradeoff and Snapback-Free RC-IGBT With P⁺ Pillars.
33. Graded-channel junctionless dual-gate MOSFETs for radiation tolerance
34. A Charge-Plasma-Based Transistor With Induced Graded Channel for Enhanced Analog Performance
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