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Experimental heavy-ion responses of 3-kV charge-balanced (CB) SiC power devices are compared with those of 3.3-kV planar SiC devices. The devices are similar, except the epitaxial region of the CB devices is heavily doped compared with the planar devices. The higher doping in the epitaxial region results in loweron-resistance, but typically leads to a lower threshold drain voltage at which single-event burnout (SEB) occurs. The experimental results demonstrate, however, that the CB devices have a similar SEB threshold to the planar devices due to the improved electric field distribution.

The total-ionizing dose (TID) response of a 5-nm bulk FinFET technology is evaluated through static random access memory (SRAM) arrays. Single-port (SP) and two-port (TP) SRAM arrays are exposed to 10-keV X-ray TID in grounded and biased conditions. The effects of TID are measured as changes in the data retention voltage ( $V_{\mathrm {DR}}$ ), or the lowest voltage at which an SRAM cell is able to retain written data. Results show that TID exposures lead to increases in average $V_{\mathrm {DR}}$ for cells/arrays. Although the average $V_{\mathrm {DR}}$ value increases after irradiation, individual cells experience varying levels of changes in $V_{\mathrm {DR}}$ . Degradation in average $V_{\mathrm {DR}}$ values is lower for parts that were grounded during irradiation compared to those that were operated at a nominal operating voltage. TP SRAM cells show greater degradation than SP cells for the same bias and input conditions during irradiation due to a higher number of transistors connected to the storage nodes. Single-event upset (SEU) rates do not change significantly across TID exposure.

Single-port (SP) and two-port (TP) static random access memory (SRAM) arrays in a commercial 5-nm FinFET technology were exposed to alpha particles at ambient and elevated temperatures up to 100 °C. Results show that increasing operating temperatures of these devices leads to significant changes in single-event upset (SEU) cross sections and multicell upset rates. Technology computer-aided design (TCAD) simulations are used to investigate the changes in charge collection and its relationship with changes in restoring current to affect storage node susceptibility. Simulations show that diffusion charge collection increases significantly for low LET particles incident outside drain regions of storage nodes. However, increasing drive current with temperature for FinFET transistors leads to decreasing SEU cross section for temperatures rising from 25 °C to 75 °C. Differences in charge collection and capacitance between SP and TP cell designs lead to decreasing SEU cross section for SP cells and increasing cross section for TP cells as temperature increases to 100 °C. These changes in vulnerability may lead to inaccurate predictions from accelerated testing at ambient temperatures if real operational temperatures are different.

This study investigated the relationship between laboratory-based electrical characterizations of process-induced variations and the sensitivity to single-event effects of static random access memory (SRAM) cells at the 5-nm bulk FinFET technology node. While previous research suggested the possibility of ranking ICs’ SE response based on electrical characterizations without using radiation beams, this study reevaluated the practicality of this approach for advanced FinFET nodes with reduced variations in process-related parameters and critical charge across SRAM cells. Laboratory-based electrical tests were conducted to measure the data retention voltages of individual SRAM bit cells for the characterization of process variations. Two types of SE tests, alpha particle and low-energy proton tests, were performed, and their results were compared with the electrical characterizations. Through statistical and spatial analyses, the study showed that the low critical charge variations at the 5-nm bulk FinFET node masked the effects of intradie and intrawafer process variations during irradiations, making it difficult to perceive the SE response of individual SRAM bit cells and entire SRAM arrays. These findings indicate that laboratory-based electrical characterizations alone cannot effectively differentiate ICs’ SE response at this advanced FinFET process.

This article presents a circuit design for measuring and emulating radiation-induced photocurrent pulses in dense, highly scaled integrated circuits (ICs) and experimental results from an implementation in a 45-nm partially depleted silicon-on-insulator (PD-SOI) process. This photocurrent measurement circuit (PMC) expands upon other work by introducing new capabilities and measurement procedures, including a method for capturing arbitrarily long pulses and an arbitrary-waveform generator (AWG) that enables flexible built-in self-test (BIST) capabilities as well as emulation of transient radiation events. Experimental PMC measurements of currents generated by flash X-ray irradiation, pulsed-laser irradiation, and AWG emulation show excellent agreement and are corroborated by technology computer-aided design (TCAD) simulations; in particular, AWG recreations of experimental flash X-ray photocurrent responses match the original data with as little as 1.375% mean absolute percentage error (MAPE). Comparisons of different transistor structures also indicate a relatively insignificant photocurrent response in body-tied devices, suggesting that floating body effects are a dominant factor for this process. Holistically, these results demonstrate the efficacy of the PMC.

The importance of including secondary particles in particle environments for single event effects (SEE) simulations is examined by comparing total error rates with and without secondary alpha particles as a result of target fragmentation. Previous experimental single-event tests have demonstrated importance of short-range, high-LET secondary particles, produced by target fragmentation near to device. However, current error rate prediction workflows, based on tools such as CREME96 and SPENVIS, do not account for these secondary particles from target fragmentation. Reevaluating those practices shows that the impact of secondary alpha particles on total error rates is negligible for the environments, devices, and aluminum shielding explored. To compare the broader issue of nuclear reactions in overlaying materials, energy deposition simulations were done in MRED, which indicate that the composition and sequence of overlying materials need to be considered with regard to secondary particle production.

Single-event burnout (SEB) and single-event leakage current (SELC) behavior of 1200 and 3300 V silicon carbide (SiC) power devices are analyzed based on heavy-ion irradiation tests. Both SEB and SELC degradation thresholds are improved in the 3300 V devices by at least 300 V compared to the 1200 V devices. Additionally, it was demonstrated that the measured SEB threshold is a strong function of the device bias and irradiation history and that bias and irradiation steps at intermediate voltages between the charge collection region and SEB region can result in parametric failure from accumulated leakage current rather than catastrophic failure by burnout.

In this work, single-event upset (SEU) and single-event transient (SET) responses of digital logic in a planar 22 nm conventional-well fully depleted silicon-on-insulator (FD-SOI) technology under various test conditions are presented. The D-flip-flop (DFF) shift registers used for the SEU experiments are more sensitive to upsets when data are dynamically loaded in during irradiation rather than statically stored beforehand, but the clock rate used to load the data does not affect the upset cross sections in any significant way. The digital pattern loaded also affects the upset cross sections, but which cross section is greater between patterns of all “1s” and all “0s” is observed to be opposite for dynamic and static tests. A key capability of the technology studied in this work is the ability to apply biases to the back gates of transistors to alter threshold voltage. For conventional-well designs, as in this work, reverse body bias can be applied, increasing the threshold voltage and decreasing leakage current. Analyzing the effects of applying a back-gate bias on SEU cross section reveals no clear trend for SEU cross sections in the DFF shift registers but applying back-gate bias decreased the SET cross sections measured from an inverter chain by as much as an order of magnitude. Supplementary SPICE-level simulations suggest that the drastic decrease in SET cross section results from attenuation in the inverter chain. The presented experimental and simulation results indicate relatively small single-event cross sections compared to other technologies reported in the literature.

Silicon carbide (SiC) power devices may exhibit step increases in leakage current when exposed to heavy ions while biased in the OFF state. Estimating the magnitude of this phenomenon over time in the variable solar energetic particle environment represents a challenge, as the probability of occurrence and step sizes are widely variable. The Prediction of Solar particle Yields for Characterizing Integrating Circuits (PSYCHIC) code is used to generate potential environmental flux spectra. Using an existing method, leakage current increases during broad-beam irradiation are characterized by frequency and magnitude. In this article, these characterizations are applied to various environmental flux spectra to generate a range of cumulative leakage current increases. This process is repeated to produce distributions of leakage current increases that account for environmental variability and step size variability. Comparing the results for various operating voltages, mission durations, and shielding, it is shown that shielding thickness and operating voltage have a significant influence on the potential cumulative leakage current increase.