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We construct binary codes for fingerprinting digital documents. Our codes for n users that are -secure against c pirates have length O(c² log(n/ϵ)). This improves the codes proposed by Boneh and Shaw [1998] whose length is approximately the square of this length. The improvement carries over to works using the Boneh-Shaw code as a primitive, for example, to the dynamic traitor tracing scheme of Tassa [2005]. By proving matching lower bounds we establish that the length of our codes is best within a constant factor for reasonable error probabilities. This lower bound generalizes the bound found independently by Peikert et al. [2003] that applies to a limited class of codes. Our results also imply that randomized fingerprint codes over a binary alphabet are as powerful as over an arbitrary alphabet and the equal strength of two distinct models for fingerprinting. [ABSTRACT FROM AUTHOR]

Frameproof codes (FPCs) are widely studied as they are classic fingerprinting codes that can protect copyrighted materials. The main interests are construction methods and bounds of the number of codewords of FPCs for a fixed length when the alphabet size approaches infinity. In this paper, we focus on the upper bound of the size of FPCs when the fixed length is 4 and the strength is 2. We obtain an upper bound 2q2-2q+7 on the size of a q-ary 2-FPC of length 4 for any positive integer q>48. The best previously well known bound of this type of FPCs is 2q2-2, which is due to Blackburn (SIAM J Discret Math 16:499-510, 2003). Our new upper bound improves the previous upper bound and it is not very far from the current best lower bound 2q2-4q+3 obtained from the explicit construction due to Chee and Zhang (IEEE Trans Inf Theory 58:5449-5453, 2012). [ABSTRACT FROM AUTHOR]

The binary-coded decimal (BCD) being the more accurate and human-readable representation with ease of conversion is prevailing in the computing and electronic communication. In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity O(N(log2b)+(N-1)), where N = number of digits and b = number of bits in a digit. BCD adder is more effective with a lookup table (LUT)-based design, due to field programmable gate array (FPGA) technology’s enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper. The proposed parallel BCD adder gains a radical achievement compared to the existing best known LUT-based BCD adders. The proposed BCD adder is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a -3 speed grade by using ISE 13.1. The proposed BCD adder provides prominent better performance with 20.0% reduction in area and 41.32% reduction in delay for the post-layout simulation. Since the proposed circuit is improved in both area and delay parameter, it is 53.06% efficient in terms of area-delay product compared to the best known existing BCD adder, which is surely a significant achievement. Moreover, the proposed design consumes 34.28% less power in comparison with existing best known approach at a clock frequency of 200 MHz and a reference voltage of 5 V. [ABSTRACT FROM AUTHOR]

The paper presents a synthesis strategy oriented to the implementation of multi-output functions into LUT-based FPGA. The key elements of the proposed method include the decomposition of multi-output functions and a technology mapping strategy. The essence of the proposed approach is based on searching for an appropriate decomposition path and the idea of cosharing logic resources. In the process of looking for cosharing logic resources, the algorithm which searches for equivalence classes plays a vital role, and is implemented on the basis of proposed modifications of BDD diagrams. The results obtained were compared with synthesis results from competitive methods. [ABSTRACT FROM AUTHOR]

The world of computing is in transition. As chips become smaller and faster, they dissipate more heat, in turn more energy is consumed. Reversible logic is gaining significance in the context of emerging technologies such as quantum computing. Reversible circuits have one-to-one mapping between the inputs and outputs. Hence, there is no loss of energy. Reversible circuits are of high interest in low-power CMOS design, optical computing, nano technology, and quantum computing. In this work, we present designs of reversible Binary Coded Decimal (BCD) adder and unified reversible BCD addition/subtraction circuit. We propose three design approaches for BCD addition. The proposed designs 1 and 2 are aimed at optimizing Garbage Outputs. The proposed design 3 outperforms in all the performance parameters along with producing zero Garbage Outputs compared to proposed designs 1 and 2. We present digit reversible BCD addition/subtraction circuit using proposed design 3 for BCD addition to get the benefit of performance parameter optimization. This design outperforms existing counterparts. [ABSTRACT FROM AUTHOR]

Decimal multiplication is a ubiquitous operation which is inherently complex in terms of partial product generation and accumulation. In this paper, the authors propose a generalized design approach and architectural framework for ‘digit-by-digit’ multiplication. Decimal partial products are generated in parallel using fast and area efficient BCD digit multipliers and their reduction is achieved using hybrid multi-operand binary-to-decimal converters. In contrast to most of the previous implementations, which propose changes either in partial product generation or reduction, this work proposes modifications at both partial product generation and reduction stages resulting in an improved performance. A comprehensive analysis of synthesis results (consistent with IEEE-compliant 16-digit decimal multiplier architecture) indicates an improvement in delay of 8–29% and a reduced area-delay product of 4–38% compared to similar work published previously. [ABSTRACT FROM AUTHOR]

A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature. [ABSTRACT FROM PUBLISHER]

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition. [ABSTRACT FROM AUTHOR]

Binary translation acts as a main method used to solve software compatibility among different instruction set architectures (ISAs), yet the main objects that the binary translator deals with are serial programs but not parallel programs. We propose a hybrid method combining local library replacement and instruction translation based on a formal model built to describe the equivalent when migrating MPI programs between different clusters. The shared codes in a MPI program (MPI library function call) are treated by executing local libraries, and the other parts are done by dynamic binary translation. Also, during the course of dealing with local library functions, we propose a method of program flow redirection by designing two algorithms along with hierarchically encapsulating local libraries. A framework called MPI-QEMU is designed to implement migrating MPI program of 64 bits from X86-64/Linux platform to the domestic SW platform which is verified by experiment. [ABSTRACT FROM AUTHOR]

Traditional projection environments typically comprise projectors and custom-built projection screens in a static setting. However, with the availability of embedded and standalone pico-projectors, the representative use-case of such hand-held projectors is shifting from static to mobile. Users are increasingly using such devices to project content in random indoor environments that are cluttered and hence not completely suitable for projection. This paper proposes a robust binary-coded pattern that enables the reliable selection of a clutter-free sub-surface from within the projected area and thus allows the confinement of projection to the selected sub-region. Experiments confirm that the proposed pattern provides better resilience to the detection errors as compared to the state-of-the-art binary-coded patterns for the case of mobile-grade low-resolution pico-projectors. [ABSTRACT FROM AUTHOR]

Decimal X\times Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix- 10~X multiples. Some works require only [ 0, 5 ]\times X via recoding digits of Y to one-hot representation of signed digits in $ [-5, 5]$ . This reduces the selection logic at the cost of one extra IPP. Two’s complement signed-digit (TCSD) encoding is often used to represent IPPs, where dynamic negation (via one xor per bit of $X$ multiples) is required for the recoded digits of $Y$ in $[-5, -1]$ . In this paper, despite generation of 17 IPPs, for 16-digit operands, we manage to start the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we save 75% of negating xors via representing precomputed multiples by sign-magnitude signed-digit (SMSD) encoding. For the first-level PPR, we devise an efficient adder, with two SMSD input numbers, whose sum is represented with TCSD encoding. Thereafter, multilevel TCSD 2:1 reduction leads to two TCSD accumulated partial products, which collectively undergo a special early initiated conversion scheme to get at the final binary-coded decimal product. As such, a VLSI implementation of $16\times 16$ -digit parallel decimal multiplier is synthesized, where evaluations show some performance improvement over previous relevant designs. [ABSTRACT FROM AUTHOR]

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits' logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems. [ABSTRACT FROM AUTHOR]

The quantum-dot cellular automata (QCA) technology is promising to overcome the limits of CMOS technology for perspective computers. A chain of QCA is used as a wire. Logic gates are simply implemented by a cross pattern of QCA. Because the leading role of QCA wires, the serial data transfer/processing is preferable. The growing market of financial, Internet-based, and automatic control computer applications requires a binary-coded decimal data encoding for direct processing of decimal information without representation and conversion errors. The 5-bit decimal Johnson–Mobius encoding and radical departure from Boolean logic allow using a delay element, implemented by short length of QCA wire, as a function element. The previous published by author serial decimal QCA arithmetic designs demonstrate hardware simplification in comparison with traditional designs. The paper presents novel serial decimal adder and adder/subtractor designs used the run-time reconfigurable wiring approach, which results in further significant QCA hardware simplification. [ABSTRACT FROM AUTHOR]

Agricultural irrigation is highly important in crop production everywhere in the world. The most important factor in irrigation is water management. Therefore it is a need to make a system which plays essential role in agricultural field to allow us to operate the water flow, the time required of the water as per the requirement without much effort. The demand for new water saving and time saving techniques in irrigation is increasing rapidly right now. [ABSTRACT FROM AUTHOR]

As stated in (7), binary coded computer programs can be shown as a metric space. Therefore, they can be measured by metric in a sense of metric space theory. This paper presents the proof that Fréchet metric is a metric on the space of all sequences of elements M={0,1t} Therefore, it is usable to build a system of software metrics based on the metric space theory [ABSTRACT FROM AUTHOR]

Partial product generation (PPG), in radix-10 multiplication hardware, is often done through selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA realization of classical PPG via digit-by-digit multiplication has recently attracted some researchers. For example, a sequential multiplier, squarer, divider, FPGA parallel multiplier, and array multiplier are all based on a specific binary-coded decimal (BCD) digit multiplier (BDM). Most BDMs, as we have encountered, compute the binary product of two 1-digit BCD operands, and convert it to 2-digit BCD product. We provide our own version of two of these works with some adjustments and improvements, and offer two new low-cost BDMs in this category. However, a recent FPGA BDM uses straightforward truth table approach from scratch and skips binary product generation. We redesign the latter via low-level FPGA programming, and also provide its ASIC realization. We synthesize all the studied and new designs on ASIC and FPGA platforms, exhaustively check them for correctness, and compare their performance, to show that our two new designs, and the ASIC and new FPGA realizations of the aforementioned fully truth table-based design, outperform the previous ones in terms of one or more figures of merit. [ABSTRACT FROM AUTHOR]

Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c0 and no ancilla input bits, and (ii) one with input carry c0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing. [ABSTRACT FROM AUTHOR]

In this paper we study the construction and the enumeration of binary words in $$\{0,1\}^*$$ having more 1's than 0's and avoiding a set of cross-bifix-free patterns. We give a particular succession rule, called jumping and marked succession rule, which describes the growth of such words according to their number of ones. Moreover, the problem of associating a word to a path in the generating tree obtained by the succession rule is solved by introducing an algorithm which constructs all binary words having more 1's than 0's and then kills those containing the forbidden patterns. Finally, we give the generating function of such words according to the number of ones. [ABSTRACT FROM AUTHOR]

Abstract: Differential Evolution (DE) is a simple yet efficient global optimization algorithm. However, the standard DE and most of its variants operate in the continuous space, which cannot solve the binary-coded optimization problems directly. To tackle this problem, this paper proposes a novel modified binary differential evolution algorithm (NMBDE) inspired by the concept of Estimation of Distribution Algorithm and DE. A novel probability estimation operator is developed for NMBDE, which can efficiently maintain diversity of population and achieve a better tradeoff between the exploration and exploitation capabilities by cooperating with the selection operator. Furthermore, the parameter study of NMBDE is run and the analysis is performed to improve the global search ability and scalability of algorithm. The effectiveness and efficiency of NMBDE was verified in applications to the numerical optimization and multidimensional knapsack problems. The experimental results demonstrate that NMBDE has the better global search ability and outperforms the discrete binary DE, the modified binary DE, the discrete binary Particle Swarm Optimization and the binary Ant System in terms of accuracy and convergence speed. [Copyright &y& Elsevier]

Abstract: In this paper, VLSI array architectures for matrix inversion are studied. A new binary-coded z-path (Bi-z) CORDIC is developed and implemented to compute the operations required in the matrix inversion using the Givens rotation (GR) based QR decomposition. The Bi-z CORDIC allows both the GR vectoring and rotation mode, as well as division and multiplication to be executed in a single unified processing element (PE). Hence, a 2D (2 dimensional) array consisting of PEs with different functionalities can be folded into a 1D array to reduce hardware complexity. The Bi-z CORDIC also eliminates the arithmetic complexity of the angle quantization and formation computation that exist in the traditional CORDIC. Two mapping techniques, namely a linear mapping method and an interlaced mapping method, for mapping a 2D matrix inversion array into a 1D array are proposed and developed. Consequently two corresponding array architectures are designed and implemented. Both the architectures use the Bi-z CORDIC in their PEs and they are designed to be fully scalable and parameterizable in terms of matrix size and data wordlength. The linear mapping method is a straightforward mapping offering simple schedule and control signals. The interlaced mapping method has a more complicated schedule with complex control signals but achieves 100% or near 100% processor utilization for odd and even size matrix, respectively. [Copyright &y& Elsevier]

Abstract: The flexible architecture of evolutionary algorithms allows specialised models to be obtained with the aim of performing as other search methods do, but more satisfactorily. In fact, there exist several evolutionary proposals in the literature that play the role of local search methods. In this paper, we make a step forward presenting a specialised evolutionary approach that carries out a search process equivalent to the one of simulated annealing. An empirical study comparing the new model with classic simulated annealing methods, hybrid algorithms and state-of-the-art optimisers concludes that the new alternative scheme for combining ideas from simulated annealing and evolutionary algorithms introduced by our proposal may outperform this kind of hybrid algorithms, and achieve competitive results with regard to proposals presented in the literature for binary-coded optimisation problems. [Copyright &y& Elsevier]

By analyzing the features of heat dissipation and isolation technology, that are usually adopted in fabrication of high-voltage gate drivers, a novel gate driver IC with 700 V BCD technology was developed. The current and turn-on time of LDMOS were reduced and the processes of BCD technology were adjusted. As a result, the issues such as high power dissipation and ground floating, that restricted the development and application of such integrated circuits, could be solved. Simulation and test results show that our solution greatly improves the performance of the gate driver and its power dissipation is only about 0.4 W when operating under 400 V at 1 MHz [ABSTRACT FROM AUTHOR]

The language JavaGI extends Java 1.5 conservatively by a generalized interface mechanism. The generalization subsumes retroactive and type-conditional interface implementations, binary methods, symmetric multiple dispatch, interfaces over families of types, and static interface methods. These features make certain coding patterns redundant, increase the expressiveness of the type system, and permit solutions to extension and integration problems with components in binary form, for which previously several unrelated extensions had been suggested. This article explains JavaGI and motivates its design. Moreover, it formalizes a core calculus for JavaGI and proves type soundness, decidability of typechecking, and determinacy of evaluation. The article also presents the implementation of a JavaGI compiler and an accompanying run-time system. The compiler, based on the Eclipse Compiler for Java, offers mostly modular static typechecking and fully modular code generation. It defers certain well-formedness checks until load time to increase flexibility and to enable full support for dynamic loading. Benchmarks show that the code generated by the compiler offers good performance. Several case studies demonstrate the practical utility of the language and its implementation. [ABSTRACT FROM AUTHOR]

Binary-code genetic algorithms (BGA) have been used to obtain the optimum design for deep groove ball bearings, based on maximum fatigue life as an objective function. The problem has ten design variables and 20 constraint conditions. This method can find better basic dynamic loads rating than those listed in standard catalogues. However, the BGA algorithm requires a tremendous number of evaluations of the objective function per case to achieve convergence (e.g. about 5 200 000 for a representative case). To overcome this difficulty, a hybrid evolutionary algorithm by combining real-valued genetic algorithm (GA) with differential evolution (DE) is used together with the proper handling of constraints for this optimum design task. Findings show that the GA—DE algorithm can successfully find the better dynamic loads rating, about 1.3—11.1 per cent higher than those obtained using the traditional BGA. Moreover, the mean number of evaluations of the objective function required to achieve convergence is about 3011, using the GA—DE algorithm, as opposed to about 5 200 000 for a representative case using the BGA. Comparison shows the GA—DE algorithm to be much more effective and efficient than the BGA. [ABSTRACT FROM AUTHOR]

The author describes how he came to be employed, in 1957, as a programmer at Nelson Research Laboratories (Stafford), then the hub of the English Electric Company's software activities, at a time when the throughput of the English Electric DEUCE computer had just been potentially improved by doubling the amount of data that could be punched on each Hollerith input card, necessitating a corresponding increase in the efficiency of the decimal-to-binary conversions used by card-reading subroutines. The DEUCE delay-line store, instruction code and input–output system are described in enough detail to enable readers to understand the difficulties, and how they were resolved. [ABSTRACT FROM PUBLISHER]

We prove that arbitrary n-ary quasigroups of order 4 can be transformed into each other by successive switchings of {a, b}-components. We prove that perfect (closely packed) binary codes with distance 3 whose rank (dimension of the linear span) is greater by 1 or 2 than the rank of a linear perfect code can be taken to each other by successive switchings of i-components. [ABSTRACT FROM AUTHOR]

We show that subclasses of q-ary separable Goppa codes Γ( L, G) with L = {α ∈ GF( q): G(α) ∈ 0} and with special Goppa polynomials G( x) can be represented as a chain of equivalent and embedded codes. For all codes of the chain we obtain an improved bound for the dimension and find an exact value of the minimum distance. A chain of binary codes is considered as a particular case with specific properties. [ABSTRACT FROM AUTHOR]

A famous open problem in the theory of quantum error-correcting codes is whether or not the parameters of an impure quantum code can violate the quantum Hamming bound for pure quantum codes. We partially solve this problem. We demonstrate that there exists a threshold N(d, m) such that an arbitrary ((n, K, d))m quantum code must obey the quantum Hamming bound whenever n ≥ N (d, m). We list some values of N(d, m) for small d and binary quantum codes. [ABSTRACT FROM AUTHOR]

In this correspondence, a completed modeling of the local binary pattern (LBP) operator is proposed and an associated completed LBP (CLBP) scheme is developed for texture classification. A local region is represented by its center pixel and a local difference sign-magnitude transform (LDSMT). The center pixels represent the image gray level and they are converted into a binary code, namely CLBP-Center (CLBP_C), by global thresholding. LDSMT decomposes the image local differences into two complementary components: the signs and the magnitudes, and two operators, namely CLBP-Sign (CLBP_S) and CLBP-Magnitude (CLBP_M), are proposed to code them. The traditional LBP is equivalent to the CLBP_S part of CLBP, and we show that CLBP_S preserves more information of the local structure than CLBP_M, which explains why the simple LBP operator can extract the texture features reasonably well. By combining CLBP_S, CLBP_M, and CLBP_C features into joint or hybrid distributions, significant improvement can be made for rotation invariant texture classification. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, the traditional automatic generation control loop with modifications is incorporated for simulating automatic generation control (AGC) in restructured power system. Federal energy regulatory commission (FERC) encourages an open market system for price based operation. FERC has issued a notice for proposed rulemaking of various ancillary services. One of these ancillary services is load following with frequency control which comes broadly under Automatic Generation Control in deregulated regime. The concept of DISCO participation matrix is used to simulate the bilateral contracts in the three areas and four area diagrams. Hybrid particle swarm optimization is used to obtain optimal gain parameters for optimal transient performance. [Copyright &y& Elsevier]

Abstract: Image annotation can be formulated as a classification problem. Recently, Adaboost learning with feature selection has been used for creating an accurate ensemble classifier. We propose dynamic Adaboost learning with feature selection based on parallel genetic algorithm for image annotation in MPEG-7 standard. In each iteration of Adaboost learning, genetic algorithm (GA) is used to dynamically generate and optimize a set of feature subsets on which the weak classifiers are constructed, so that an ensemble member is selected. We investigate two methods of GA feature selection: a binary-coded chromosome GA feature selection method used to perform optimal feature subset selection, and a bi-coded chromosome GA feature selection method used to perform optimal-weighted feature subset selection, i.e. simultaneously perform optimal feature subset selection and corresponding optimal weight subset selection. To improve the computational efficiency of our approach, master-slave GA, a parallel program of GA, is implemented. k-nearest neighbor classifier is used as the base classifier. The experiments are performed over 2000 classified Corel images to validate the performance of the approaches. [Copyright &y& Elsevier]