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I/O operations are a known performance bottleneck of HPC applications. To achieve good performance, users often employ an iterative multistage tuning process to find an optimal I/O stack configuration. However, an I/O stack contains multiple layers, such as high-level I/O libraries, I/O middleware, and parallel file systems, and each layer has many parameters. These parameters and layers are entangled and influenced by each other. The tuning process is time-consuming and complex. In this work, we present TunIO, an AI-powered I/O tuning framework that implements several techniques to balance the tuning cost and performance gain, including tuning the high-impact parameters first. Furthermore, TunIO analyzes the application source code to extract its I/O kernel while retaining all statements necessary to perform I/O. It utilizes a smart selection of high-impact configuration parameters of the given tuning objective. Finally, it uses a novel Reinforcement Learning (RL)-driven early stopping mechanism to balance the cost and performance gain. Experimental results show that TunIO leads to a reduction of up to ≈73% in tuning time while achieving the same performance gain when compared to H5Tuner. It achieves a significant performance gain/cost of 208.4 MBps/min (I/O bandwidth for each minute spent in tuning) over existing approaches under our testing.

Today’s deep learning models face an increasing demand to handle dynamic shape tensors and computation whose shape information remains unknown at compile time and varies in a nearly infinite range at runtime. This shape dynamism brings tremendous challenges for existing compilation pipelines designed for static models which optimize tensor programs relying on exact shape values. This paper presents TSCompiler, an end-to-end compilation framework for dynamic shape models. TSCompiler first proposes a symbolic shape propagation algorithm to recover symbolic shape information at compile time to enable subsequent optimizations. TSCompiler then partitions the shape-annotated computation graph into multiple subgraphs and fine-tunes the backbone operators from the subgraph within a hardware-aligned search space to find a collection of high-performance schedules. TSCompiler can propagate the explored backbone schedule to other fusion groups within the same subgraph to generate a set of parameterized tensor programs for fused cases based on dependence analysis. At runtime, TSCompiler utilizes an occupancy-targeted cost model to select from pre-compiled tensor programs for varied tensor shapes. Extensive evaluations show that TSCompiler can achieve state-of-the-art speedups for dynamic shape models. For example, we can improve kernel efficiency by up to 3.97× on NVIDIA RTX3090, and 10.30 × on NVIDIA A100 and achieve up to five orders of magnitude speedups on end-to-end latency. [ABSTRACT FROM AUTHOR]

Reductions in energy consumption and greenhouse gas emissions are required globally. Under this background, the Multilayer Perceptron machine-learning algorithm was used to predict liquid natural gas consumption to improve energy consumption efficiency. Setting hyperparameters remains challenging in machine-learning-based prediction. Here, to improve prediction efficiency, hyperparameter autotuning via Bayesian optimization was used to identify the optimal combination of the eight key hyperparameters. The autotuned model was validated by comparing its predictive performance with that of a base model (with all hyperparameters set to the default values) using the coefficient of variation of root-mean-square error (CvRMSE) and coefficient of determination (R2) based on the Measurement and Verification Guideline evaluation metrics. To confirm the model's industrial applicability, its predictions were compared with values measured at a small-to-medium-sized food factory. The optimized model performed better than the base model, achieving a CvRMSE of 12.30% and an R2 of 0.94, and achieving a predictive accuracy of 91.49%. By predicting energy consumption, these findings are expected to promote the efficient operation and management of energy in the food industry. [ABSTRACT FROM AUTHOR]

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The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations. [ABSTRACT FROM AUTHOR]

The optimal setting of parameters of PID controllers is a significant requirement of industrial practice. It seems intuitive, but it can be complicated, especially when there are many (often conflicting) requirements for the control process. Many regulators are then set incorrectly or inappropriately. The search for a method of identifying the parameters of the controlled system with the subsequent setting of the parameters of the PID controllers takes place from the moment it is found. Nevertheless, we decided to develop a physical controller that would be easy to use in industrial practice. The demand is that the operator set as few parameters as possible, and most of the settings should be automatic. We based the identification on the relay method, more precisely, on its modification known as the relay-shifting method. During identification, an asymmetric relay is used. The parameters of a model of the system are then calculated from three points of the frequency characteristic. This method is not as commonly utilized in current commercial controllers. The general advantages of the relay method include identifying the system in a closed control loop and performing time-saving calculations. This makes it suitable for practical use in industry. The parameters of the PID controller are calculated using either the Marchetti-Scali method or the Ackermann method from the model whose parameters were obtained by relay identification. We built the controller on a development microcontroller board, which we supplemented with the necessary peripherals. The result is a prototype of a physical PID controller with autotuning. In the article, we present not only the implemented equations but also the test results of our PID controller on one of the real devices on which its functionality was verified.

Tuning tensor program generation involves navigating a vast search space to find optimal program transformations and measurements for a program on the target hardware. The complexity of this process is further amplified by the exponential combinations of transformations, especially in heterogeneous environments. This research addresses these challenges by introducing a novel approach that learns the joint neural network and hardware features space, facilitating knowledge transfer to new, unseen target hardware. A comprehensive analysis is conducted on the existing state-of-the-art dataset, TenSet, including a thorough examination of test split strategies and the proposal of methodologies for dataset pruning. Leveraging an attention-inspired technique, we tailor the tuning of tensor programs to embed both neural network and hardware-specific features. Notably, our approach substantially reduces the dataset size by up to 53% compared to the baseline without compromising Pairwise Comparison Accuracy (PCA). Furthermore, our proposed methodology demonstrates competitive or improved mean inference times with only 25–40% of the baseline tuning time across various networks and target hardware. The attention-based tuner can effectively utilize schedules learned from previous hardware program measurements to optimize tensor program tuning on previously unseen hardware, achieving a top-5 accuracy exceeding 90%. This research introduces a significant advancement in autotuning tensor program generation, addressing the complexities associated with heterogeneous environments and showcasing promising results regarding efficiency and accuracy. [ABSTRACT FROM AUTHOR]

Reductions in energy consumption and greenhouse gas emissions are required globally. Under this background, the Multilayer Perceptron machine-learning algorithm was used to predict liquid natural gas consumption to improve energy consumption efficiency. Setting hyperparameters remains challenging in machine-learning-based prediction. Here, to improve prediction efficiency, hyperparameter autotuning via Bayesian optimization was used to identify the optimal combination of the eight key hyperparameters. The autotuned model was validated by comparing its predictive performance with that of a base model (with all hyperparameters set to the default values) using the coefficient of variation of root-mean-square error (CvRMSE) and coefficient of determination (R2) based on the Measurement and Verification Guideline evaluation metrics. To confirm the model’s industrial applicability, its predictions were compared with values measured at a small-to-medium-sized food factory. The optimized model performed better than the base model, achieving a CvRMSE of 12.30% and an R2 of 0.94, and achieving a predictive accuracy of 91.49%. By predicting energy consumption, these findings are expected to promote the efficient operation and management of energy in the food industry.

Training with unlabeled datasets using self-supervised models has the edge over training with labeled datasets, reducing human effort, and no need for annotated data during training. The knowledge obtained from the pre-trained self-supervised model can be transferred to an image classifier as a target task. Transferring knowledge from source to target task requires tuning a large number of hyperparameters, such as number of CNN layers, number of filters in each CNN layer, kernel size, stride, number of fully connected (FC) layers, units in each FC layer, dropouts, learning rate, and many more. An efficient process is required to automatically tune these hyperparameters to reduce the manual efforts and enhance the performance of the self-supervised model. This paper uses a pre-trained self-supervised model to transfer knowledge for image classification. We propose an efficient Bayesian optimization-based method for automatically tuning (autotuning) the hyperparameters of the self-supervised model during the knowledge transfer. The proposed autotuned image classifier consists of a few CNN layers followed by an FC layer. Finally, we use a softmax layer to obtain the probability of classes for the images. To evaluate the performance of the proposed method, state-of-the-art self-supervised models such as SimClr, SWAV, and SWAV 2x are used to extract the learned features. According to our experiments on three benchmarked datasets (CIFAR-10, CIFAR-100, and Tiny Imagenet datasets), the proposed method not only enhances the performances of the self-supervised models, but also provides state-of-the-art results. [ABSTRACT FROM AUTHOR]

The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations.

The Message Passing Interface (MPI) is a crucial programming tool for enabling communication between processes in parallel applications. The goal of MPI users is to allocate tasks to processors in a way that maximizes both spatial and temporal locality in the network. However, this can be challenging, especially in large-scale networks where maximizing processor locality may not be feasible at runtime. To address this issue, we propose the use of Hamorder, an offline node reassignment approach that takes into account physical processor locations based on graph reordering for Random network topologies. Hamorder aims to optimize task mapping for improved performance in parallel applications, whether for multiple tasks or within a single task. Additionally, we investigate the potential of improving MPI applications through runtime parameter tuning based on Hamorder. Our evaluation results show that Hamorder provides a 27.3% improvement in performance compared to the Gorder algorithm on Random topologies, which is a state-of-the-art solution designed with the aim of enhancing cache locality and achieves this goal by rearranging the vertices of a graph in a way that places the vertices that are typically accessed together in close proximity. Moreover, our autotuning framework using Hamorder results in an average speedup of $1.38\times $ for targeted MPI applications by searching through various runtime parameter combinations.

This article presents an automated, model-free, data-driven method for the safe tuning of PID cascade controller gains based on Bayesian optimization. The optimization objective is composed of data-driven performance metrics and modeled using Gaussian processes. The safety requirement is imposed via a barrier-like term in the objective, which is introduced to account for operational changes in the system. We further introduce a data-driven constraint that captures the stability requirements from system data. Numerical evaluation shows that the proposed approach outperforms relay feedback autotuning and quickly converges to the global optimum, thanks to a tailored stopping criterion. We demonstrate the performance of the method through simulations and experiments. For experimental implementation, in addition to the introduced safety constraint, we integrate a method for automatic detection of the critical gains and extend the optimization objective with a penalty depending on the proximity of the current candidate points to the critical gains. The resulting automated tuning method optimizes system performance while ensuring stability and standardization. [ABSTRACT FROM AUTHOR]

This article presents Kadabra, a Java source-to-source compiler that allows users to make code queries, code analysis and code transformations, all user-programmable using the domain-specific language LARA. We show how Kadabra can be used as the basis for developing a runtime autotuning and adaptivity framework, able to adapt existing source Java code in order to take advantage of runtime autotuning. Specifically, this article presents the framework, consisting of Kadabra and an API for runtime adaptivity. We show the use of the framework to extend Java applications with autotuning and runtime adaptivity mechanisms to target performance improvement and/or energy saving goals.

Kernel Tuning Toolkit (KTT) is an autotuning framework for CUDA, OpenCL and Vulkan kernels. KTT provides advanced autotuning features such as support for both dynamic (online) and offline tuning, and an ability to tune multiple kernels together with shared tuning parameters. Furthermore, it offers customization features that make integration into larger software suites possible. The framework handles all major steps required for autotuning implementation, including configuration space creation and exploration, kernel code execution and output validation. The public API is available natively in C++ and via bindings in Python.

Tuning tensor program generation involves navigating a vast search space to find optimal program transformations and measurements for a program on the target hardware. The complexity of this process is further amplified by the exponential combinations of transformations, especially in heterogeneous environments. This research addresses these challenges by introducing a novel approach that learns the joint neural network and hardware features space, facilitating knowledge transfer to new, unseen target hardware. A comprehensive analysis is conducted on the existing state-of-the-art dataset, TenSet, including a thorough examination of test split strategies and the proposal of methodologies for dataset pruning. Leveraging an attention-inspired technique, we tailor the tuning of tensor programs to embed both neural network and hardware-specific features. Notably, our approach substantially reduces the dataset size by up to 53% compared to the baseline without compromising Pairwise Comparison Accuracy (PCA). Furthermore, our proposed methodology demonstrates competitive or improved mean inference times with only 25–40% of the baseline tuning time across various networks and target hardware. The attention-based tuner can effectively utilize schedules learned from previous hardware program measurements to optimize tensor program tuning on previously unseen hardware, achieving a top-5 accuracy exceeding 90%. This research introduces a significant advancement in autotuning tensor program generation, addressing the complexities associated with heterogeneous environments and showcasing promising results regarding efficiency and accuracy.

Parallel Input output is an essential component of modern high-performance computing (HPC). Obtaining good I/O performance for a broad range of applications on diverse HPC platforms is a major challenge, in part, because of complex inter dependencies between I/O middleware and hardware. The parallel file system and I/O middleware layers all offer optimization parameters that can, in theory, result in better I/O performance. Unfortunately, the right combination of parameters is highly dependent on the application, HPC platform, problem size, and concurrency. Scientific application developers do not have the time or expertise to take on the substantial burden of identifying good parameters for each problem configuration. They resort to using system defaults, a choice that frequently results in poor I/O performance. We expect this problem to be compounded on exascale-class machines, which will likely have a deeper software stack with hierarchically arranged hardware resources. We present as a solution to this problem an autotuning system for optimizing I/O performance, I/O performance modeling, I/O tuning, and I/O patterns. We demonstrate the value of this framework across several HPC platforms and applications at scale.

Many computational problems consider memory throughput a performance bottleneck, especially in the domain of parallel computing. Software needs to be attuned to hardware features like cache architectures or concurrent memory banks to reach a decent level of performance efficiency. This can be achieved by selecting the right memory layouts for data structures or changing the order of data structure traversal. In this work, we present an abstraction for traversing a set of regular data structures (e.g., multidimensional arrays) that allows the design of traversal-agnostic algorithms. Such algorithms can easily optimize for memory performance and employ semi-automated parallelization or autotuning without altering their internal code. We also add an abstraction for autotuning that allows defining tuning parameters in one place and removes boilerplate code. The proposed solution was implemented as an extension of the Noarr library that simplifies a layout-agnostic design of regular data structures. It is implemented entirely using C++ template meta-programming without any nonstandard dependencies, so it is fully compatible with existing compilers, including CUDA NVCC or Intel DPC++. We evaluate the performance and expressiveness of our approach on the Polybench-C benchmarks. • Proposing novel abstraction for flexible traversals of regular data structures. • Designed for traversal-agnostic algorithms in HPC parallel computing. • Reduces traversal code complexity, improving separation of concerns and reusability. • Including autotuning abstraction that simplifies tuning in a declarative way. • Implemented in Noarr library uses plain C++ and requires no DSL pre-compilation. [ABSTRACT FROM AUTHOR]

Automatic parallelization of sequential programs combined with auto-tuning is an alternative to manual parallelization. With wider research directions and the increased number of performance tuning tools that have been developed, it has become increasingly difficult to choose a particular tuning tool. This paper reviews the fundamentals of different performance optimization and tuning techniques. It also surveys several tuning frameworks and classifies them into different groups based on their criteria. Developing benchmarks for HPC and validating their accuracy are demanding tasks for computer architects, researchers, and application developers. In addition to providing a survey of performance-tuning tools, we also performed a detailed review of current benchmarks and discussed the requirements for future benchmarks. We performed a detailed comparison of these tuning tools based on other features such as speedup and infrastructure details. We believe that this study will be a very useful resource for parallel computing communities, especially for early-stage parallel computing and performance researchers to gain exposure to existing performance optimization options.

PARCSIM is a parallel software simulator that allows a user to capture, through a graphical interface, matrix algorithm schemes that solve scientific problems. With this tool, the user can analyse the execution times that would be obtained by using different spatio-temporal mapping of computational tasks on available computational units, parallelism parameters and computational libraries. Furthermore, for complex problem models, the self-optimization engine incorporated in this tool analyses the huge tree of possible calculations grouping and mapping strategies in search of the choice that makes the best use of the available hardware resources. This tool also offers polyalgorithmic resolution by making automatically the best decision between different software approaches to solve a given problem on the hardware system available. This work shows the usefulness of this simulator to efficiently solve hierarchical problems constructed from previously modelled subproblems. This task is performed by reusing, in a scalable way, the optimization information of these subproblems to establish the best execution configuration for the composite problem. [ABSTRACT FROM AUTHOR]

We develop a ytopt autotuning framework that leverages Bayesian optimization to explore the parameter space search and compare four different supervised learning methods within Bayesian optimization and evaluate their effectiveness. We select six of the most complex PolyBench benchmarks and apply the newly developed LLVM Clang/Polly loop optimization pragmas to the benchmarks to optimize them. We then use the autotuning framework to optimize the pragma parameters to improve their performance. The experimental results show that our autotuning approach outperforms the other compiling methods to provide the smallest execution time for the benchmarks syr2k, 3mm, heat‐3d, lu, and covariance with two large datasets in 200 code evaluations for effectively searching the parameter spaces with up to 170,368 different configurations. We find that the Floyd–Warshall benchmark did not benefit from autotuning. To cope with this issue, we provide some compiler option solutions to improve the performance. Then we present loop autotuning without a user's knowledge using a simple mctree autotuning framework to further improve the performance of the Floyd–Warshall benchmark. We also extend the ytopt autotuning framework to tune a deep learning application. [ABSTRACT FROM AUTHOR]

GPUs, with their high bandwidths and computational capabilities are an increasingly popular target for scientific computing. Unfortunately, to date, harnessing the power of the GPU has required use of a GPU-specific programming model like CUDA, OpenCL, or OpenACC. As such, in order to deliver portability across CPU-based and GPU-accelerated supercomputers, programmers are forced to write and maintain two versions of their applications or frameworks. In this paper, we explore the use of a compiler-based autotuning framework based on CUDA-CHiLL to deliver not only portability, but also performance portability across CPU- and GPU-accelerated platforms for the geometric multigrid linear solvers found in many scientific applications. We show that with autotuning we can attain near Roofline (a performance bound for a computation and target architecture) performance across the key operations in the miniGMG benchmark for both CPU- and GPU-based architectures as well as for a multiple stencil discretizations and smoothers. We show that our technology is readily interoperable with MPI resulting in performance at scale equal to that obtained via hand-optimized MPI+CUDA implementation.

GPUs, with their high bandwidths and computational capabilities are an increasingly popular target for scientific computing. Unfortunately, to date, harnessing the power of the GPU has required use of a GPU-specific programming model like CUDA, OpenCL, or OpenACC. As such, in order to deliver portability across CPU-based and GPU-accelerated supercomputers, programmers are forced to write and maintain two versions of their applications or frameworks. In this paper, we explore the use of a compiler-based autotuning framework based on CUDA-CHiLL to deliver not only portability, but also performance portability across CPU- and GPU-accelerated platforms for the geometric multigrid linear solvers found in many scientific applications. We show that with autotuning we can attain near Roofline (a performance bound for a computation and target architecture) performance across the key operations in the miniGMG benchmark for both CPU- and GPU-based architectures as well as for a multiple stencil discretizations and smoothers. We show that our technology is readily interoperable with MPI resulting in performance at scale equal to that obtained via hand-optimized MPI+CUDA implementation.

Possible dynamic interactions among multiple dc microgrid power converters that are connected to a common dc bus can lead to performance degradation or even stability issues in some control loops. Thus, in order to maintain a desired dynamic behavior when operating conditions or system parameters are changing, an interesting approach is to adopt autotuning for the controller parameters. In general, existing autotuning methods are based on the evaluation of the stability specifications (e.g., the crossover frequency and the phase margin) and the adaptation of the controller to ensure the specified dynamic properties. However, the desired bandwidth and phase margin may not be achievable due to parameter changes, unexpected additional delays, or unmodeled dynamics in the feedback loop. This article addresses the infeasibility issue by adding an external control loop on top of the autotuning unit. This external loop adjusts the reference crossover frequency until the phase margin specification is fulfilled. As a result, the proposed scheme is capable of tracking the highest bandwidth at which the reference phase margin is achievable, i.e., the maximum allowable bandwidth. The proposed method is applied to a dc microgrid prototype, and the simulation and experimental results are discussed. [ABSTRACT FROM AUTHOR]

In this article, we propose a performance-based autotuning method for cascade control systems, where the parameters of a linear axis drive motion controller from two control loops are tuned jointly. Using Bayesian optimization as all parameters are tuned simultaneously, the method is guaranteed to converge asymptotically to the global optimum of the cost. The data-efficiency and performance of the method are studied numerically for several training configurations and compared numerically to those achieved with classical tuning methods and to the exhaustive evaluation of the cost. On the real system, the tracking performance and robustness against disturbances are compared experimentally to nominal tuning. The numerical study and the experimental data both demonstrate that the proposed automated tuning method is efficient in terms of required tuning iterations, robust to disturbances, and results in improved tracking. [ABSTRACT FROM AUTHOR]

In this article, increment count method (ICM) is proposed as a novel approach for simultaneous steady-state detection and transportation time delay estimation for industrial processes. The concept of ICM is presented, and its implementation issues are discussed. Especially, the simplicity and very low computational complexity of ICM are addressed, which support its practical implementation. Then, as a practical example, ICM is used as a part of the autotuning algorithm dedicated for reduced-order active disturbance rejection controller with Smith predictor (RADRC+SP). Jointly with dedicated optimization algorithm, it allows for identification between the first or second order of process dynamics. The results of this identification allow for effective tuning of RADRC+SP based on the novel tuning rules. The practical aspect includes programmable logic controllers (PLC) based implementation of both autotuning and RADRC+SP controller in the form of the general-purpose function blocks. The experimental validation shows the practical applicability and superiority of the proposed methods. [ABSTRACT FROM AUTHOR]

Dataflow computing allows to start computations as soon as all their dependencies are satisfied. This is particularly useful in applications with irregular or complex patterns of dependencies which would otherwise involve either coarse grain synchronizations which would degrade performance, or high programming costs. A recent proposal for the easy development of performant dataflow algorithms in hybrid shared/distributed memory systems is UPC++ DepSpawn. Among the many techniques it applies to provide good performance is a software cache that minimizes the communications among the processes involved. In this article we provide the details of the implementation and operation of this cache and we present an autotuning strategy that simplifies its usage by freeing the user from having to estimate an adequate size for this cache. Rather, the runtime is now able to define reasonably sized caches that provide near optimal behavior. [ABSTRACT FROM AUTHOR]

The execution of complex distributed applications in exascale systems faces many challenges, as it involves empirical evaluation of countless code variations and application runtime parameters over a heterogeneous set of resources. To mitigate these challenges, the research field of autotuning has gained momentum. The autotuning automates identifying the most desirable application implementation in terms of code variations and runtime parameters. However, the complexity and size of the exascale systems make the autotuning process very difficult, especially considering the number of parameter variations that have to be identified. Therefore, we introduce a novel approach for autotuning exascale applications based on a genetic multi-objective optimization algorithm integrated within the ASPIDE exascale computing framework. The approach considers multi-dimensional search space with support for pluggable objective functions, including execution time and energy requirements. Furthermore, the autotuner employs a machine learning-based event detection approach to detect events and anomalies during application execution, such as hardware failures or communication bottlenecks.

Unlike bigger aircraft, the small fixed-wing unmanned aerial vehicles face significant stability challenges in a turbulent environment. To improve the flight performance, a fixed-wing UAV with segmented aileron control surfaces has been designed and deployed. A total of four ailerons are attached to the main wing and grouped into inner and outer aileron pairs. The controllers are automatically tuned by utilizing the frequency response data obtained via the frequency sampling filter and the relay with embedded integrator experiments. The hardware validation experiments are performed in the normal and turbulent flight environments under three configurations: inner aileron pair only, outer aileron pair only and collective actuation of all the aileron pairs. The error-threshold-based control is introduced to handle collective actuation of aileron pairs. The experiments have manifested that the collective usage of all aileron segments improves the roll attitude stability by a margin of 38.69% to 43.51% when compared to the independent actuation of aileron pairs in a turbulent atmosphere.

Today's stream processing systems handle high-volume data streams in an efficient manner. To achieve this goal, they are designed to scale out on large clusters of commodity machines. However, despite the efficient use of distributed architectures, they lack support to co-processors like graphical processing units (GPUs) ready to accelerate data-parallel tasks. The main reason for this lack of integration is that GPU processing and the streaming paradigm have different processing models, with GPUs needing a bulk of data present at once while the streaming paradigm advocates a tuple-at-a-time processing model. This paper contributes to fill this gap by proposing Gasser, a system for offloading the execution of sliding-window operators on GPUs. The system focuses on completely general functions by targeting the parallel processing of non-incremental queries that are not supported by the few existing GPU-based streaming prototypes. Furthermore, Gasser provides an auto-tuning approach able to automatically find the optimal value of the configuration parameters (i.e., batch length and the degree of parallelism) needed to optimize throughput and latency with the given query and data stream. The experimental part assesses the performance efficiency of Gasser by comparing its peak throughput and latency against Apache Flink, a popular and scalable streaming system. Furthermore, we evaluate the penalty induced by supporting completely general queries against the performance achieved by the state-of-the-art solution specifically optimized for incremental queries. Finally, we show the speed and accuracy of the auto-tuning approach adopted by Gasser, which is able to self-configure the system by finding the right configuration parameters without manual tuning by the users.