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Copyright of Journal of Computer-Aided Design & Computer Graphics / Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao is the property of Gai Kan Bian Wei Hui and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With the reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests. By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of autonomous of the plan estimate conjointly gives an extra on-chip investigating flag permeability for each enrols. It is in reverse congruous to the standard full check plans and with a minor improvement existing test design generators and test systems can be utilized conjointly talked about for the arrangement of including built-in self-test (BIST) and gigantic parallel check chains with the proposed plan. The design and implementation of single cycle access test structure for logic test is functionally verified using Vivado. The pre layout and post layout synthesis and its physical design are performed using cadence Genus and Innonus tools respectively, with the optimized area, power, and delay. [ABSTRACT FROM AUTHOR]

Accelerators for machine learning [artificial intelligence (AI)] inferencing applications are homogeneous designs composed of identical cores. Each core or processing element (PE) contains multiply-and-accumulate units, control logic, and registers for storing and forwarding weights and activations. Testing homogeneous array-based AI accelerator chips by running automatic test pattern generation (ATPG) at the array level results in a high CPU time and pattern count. We propose a constant-testable (C-testable) method for test generation at the PE level such that the ATPG effort does not increase with the number of PEs. Our results show that compared to the traditional array-level testing, the proposed method achieves up to $4.2\times $ ($3.5\times $), $1530\times $ ($2388\times $), and $170\times $ ($142\times $) reduction in the test pattern count, ATPG runtime, and test cycle count, respectively, for stuck-at (transition) faults in a $256\times 256$ array, while preserving the test coverage. A reconfigurable scan architecture is introduced to enable the proposed C-testable solution for the entire accelerator array. The design-space exploration of a hierarchical test-compaction framework is presented. We also describe four debug solutions for fault localization and diagnosis. [ABSTRACT FROM AUTHOR]

Trends in the automotive industry confirm that the demand for testing of embedded systems, especially advanced driver assistance systems (ADAS), will grow dramatically in the near future. This paper proposes a new solution that automates the detection of software defects in embedded systems. The solution consists of a data-driven sampling algorithm to intelligently sample the testing space by sequentially generating test cases. Moreover, it segregates different defects from each other and identifies the signals that trigger each. The results are compared against other automated methods for defect identification and analysis, and it is found that this novel solution is able to identify defects more rapidly. In addition, it correctly separates defects and reliably reproduces each distinct defect. [ABSTRACT FROM AUTHOR]

Abstract Due to integrated circuit (IC) production chain globalisation, several new threats such as hardware trojans, counterfeiting and overproduction are threatening the IC industry. So logic locking is deployed to hinder these security threats. In this technique, an IC is locked, and its functionality is retrieved when the right key is loaded onto it. We propose ‘noise‐based’ logic locking, consisting of two separate compliment blocks, which function in three states. By flipping a signal once in the circuit, these modules add corruption to the circuit, whereas either flipping the same signal twice or not flipping leads to the correct functionality. Thus, a low probability skew with a low corruption in the output is obtained by utilisation of these flipping states. We have improved SAT attack resiliency based on time by 17% for a locking block with 14 primary inputs in comparison with the well‐known anti‐SAT. The area overhead is less in comparison with other schemes, in which extra dummy parts or obfuscation elements are added to their circuit. Also, more crucially, our locking blocks are immune to SPS attack solely. After executing various attacks, retrieved circuits indicate improved overall resiliency against automatic test pattern generation based and approximate guided removal attacks as well.

Abstract The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic‐0 and logic‐1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With the reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests. By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of autonomous of the plan estimate conjointly gives an extra on-chip investigating flag permeability for each enrols. It is in reverse congruous to the standard full check plans and with a minor improvement existing test design generators and test systems can be utilized conjointly talked about for the arrangement of including built-in self-test (BIST) and gigantic parallel check chains with the proposed plan. The design and implementation of single cycle access test structure for logic test is functionally verified using Vivado. The pre layout and post layout synthesis and its physical design are performed using cadence Genus and Innonus tools respectively, with the optimized area, power, and delay. [ABSTRACT FROM AUTHOR]

Approximate computing (AxC) is increasingly emerging as a new design paradigm to produce more efficient computation systems by judiciously reducing the computation quality. In particular, AxC has been successfully applied to integrated circuits (ICs), in the last years. Hence, concerning the test of such new class of ICs, namely approximate ICs (AxICs), new challenges—as well as new opportunities—have emerged. In this survey, we provide a thorough analysis of issues related to test procedures for AxICs and review the state-of-the-art techniques to deal with them. We resort to an illustrative example having the twofold aim of: 1) guiding the reader through the AxIC testing challenges and 2) illustrating the existing solutions to correctly overcome them, while suitably taking advantage of opportunities coming from approximation. We analyze experimentally the most recent testing techniques for AxICs and highlight their mature aspects, as well as their shortcomings. Experimental outcomes show that the testing process for AxIC is not completely mature. Indeed, only under specific conditions existing testing procedures achieve good results. [ABSTRACT FROM AUTHOR]

Test stimulus generation algorithms for analog/RF circuits rely on iterative simulation of the circuits concerned and are extremely computation-intensive. Our objective is to speed up test stimulus generation while allowing tests to be optimized dynamically (adapted) across diverse process corners that a device under test (DUT) is experiencing during manufacturing without compromising test quality. To achieve this, we propose to dynamically recognize devices from unknown process corners during manufacturing test and create Booleanized models of these devices from measurements performed on hardware. The cumulative ensemble of Booleanized models across different devices is used to (re-) optimize tests depending on observed performance statistics. The use of Booleanized models for test generation allows orders of magnitude speed up in test computation time while allowing emulation of devices long after they have shipped to the customer. The method is demonstrated using the alternative test methodology developed in prior research and allows the tests concerned to adapt to process shifts in a dynamic manner during device manufacture. The simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques. [ABSTRACT FROM AUTHOR]

Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging. [ABSTRACT FROM AUTHOR]

Safety‐critical technology rests on optimised and effective testing techniques for every embedded system involved in the equipment. Pattern generator (PG) such as linear feedback shift register (LFSR) is used for fault detection and useful for reliability and online test. This study presents an analysis of the LFSR, using a known automatic test PG (ATPG) test set. Two techniques are undertaken to target difficult‐to‐detect faults with their respective trade‐off analysis. This is achieved using Berlekamp–Massey (BM) algorithm with optimisations to reduce area overhead. The first technique (concatenated) combines all test sets generating a single polynomial that covers complete ATPG set (baseline‐C). Improvements are found in Algorithm 1 reducing polynomial size through Xs assignment. The second technique uses non‐concatenated test sets and provides a group of LFSRs using BM without including any optimisation (baseline‐N). This algorithm is further optimised by selecting full mapping and independent polynomial expressions. Results are generated using 32 benchmarks and 65 nm technology. The concatenated technique provides reductions on area overhead for 90.6% cases with a best case of 57 and 39% means. The remaining 9.4% of cases, non‐concatenated technique provides the best reduction of 37 with 1.4% means, whilst achieving 100% test mapping in both cases. [ABSTRACT FROM AUTHOR]

The statistical delay of a path is traditionally modeled as a Gaussian random variable assuming that the path is always sensitized by a test pattern. Its sensitization in various circuit instances varies among its test patterns and the pattern induced delay is non-Gaussian. It is modeled using probability mass functions (PMFs). This article presents an automatic test pattern generation (ATPG) method, where multiple uncorrelated test patterns per path improve its defect coverage (DC). The impact of the ATPG process is evaluated by comparing to traditional methods. It is also shown that the presented ATPG is useful in selecting critical paths. [ABSTRACT FROM AUTHOR]

Generation of complex heap structures is required for many software testing and verification techniques, which are used to enhance software reliability. It enables them to work for programs dependent on such structures. Generating all the valid structures within a size bound is time-consuming, and it is hard to predict an input size completely generatable within a time bound. This is due to the depth-first traversal of the candidate space. However, an efficient breadth-first traversal requires a compact state encoding to store candidates for exploration in the next level. In this paper, we present present a novel state encoding technique that stores an incomplete representation of state that can be recovered during search. We build upon the Korat algorithm—demonstrated to effectively generate tests and find bugs for many software programs—and present iKorat, an incremental algorithm for breadth-first exploration of the search space. Our encoding enables a more efficient implementation of iterative deepening that avoids redundant work. Standard iterative deepening algorithms allow a breadth-first search when the underlying algorithm is depth-first by repeating the work of earlier iterations. iKorat, however, uses information from smaller sizes to avoid redundant work for larger sizes. It also enables a new technique for parallelizing Korat by communicating candidates using our encoding. piKorat generates structures of larger sizes in parallel as soon as incremental information is available from smaller sizes. Our evaluation shows that iKorat-based iterative deepening is more efficient than Korat and that piKorat naturally extends the technique for parallel generation of complex structures. [ABSTRACT FROM AUTHOR]

Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-power technology in the phase of register transfer logic design, functional verification, register transfer logic and physical synthesis and physical design. Design for test is not an exception to this. The low-power design-for-test techniques can be applied at various levels of the design-for-test flow as in the scan insertion stage, automatic test pattern generation simulations stage, testing stage, and so on. Some of the reasons for the high-power utilization in the design-for-test phase can be due to the external circuitry being inserted during the design phase and not used in the functional mode. The complete circuit will be active in the test mode only. In this paper, the focus will be primarily on reducing the power during the automatic test pattern generation scan synthesis phase. All the scan flops are connected by a common scan clock with a fixed frequency. The intention of this study is to divide the clock frequency by half and make sure that the power is reduced without affecting any timing violations. Since the scan clock frequency is low, it can be further divided to ensure that power is reduced without affecting the testing process of the chip. [ABSTRACT FROM AUTHOR]

A comprehensive test set targets the detection of several fault models. As an example, in this study, stuck‐at faults, transition faults and four‐way bridging faults are targeted. Bridging faults represent a fault model where it is necessary to select a subset of target faults from all the possible faults. After test generation for single stuck‐at faults, undetectable single stuck‐at faults can be used for identifying undetectable transition and four‐way bridging faults. These faults can be removed from the sets of target faults to reduce the test generation effort. The new contribution of the study is related to the possibility of updating the set of target bridging faults again after test generation for transition faults. The analysis performed in the study leads to the premise that the presence of an undetectable or aborted transition fault on a line g makes bridging faults that are associated with line g less likely to be detected. As a result, line g may be covered by fewer bridging faults than selected for it, creating a test hole. To address this issue, the study suggests that more bridging faults should be selected for line g in this case. Experimental results are presented to support the discussion. [ABSTRACT FROM AUTHOR]

Low-power design is a key consideration in modern design. XOR self-gating (data-driven self-gating) is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. When applying XOR self-gating, dynamic power consumption is reduced, but the number of required test patterns on the testing side is inflated. In critical cases, more than three times the regular number of scan test patterns may be required for industrial designs, such as GPUs. In this brief, we propose a novel self-gating structure. Data-selectable self-gating (DSSG) is designed to use functional data and scan data selectively to eliminate the unnecessary clock toggling of flip-flops. With this structure, the self-gating function can be used in the scan test mode, as well as the function mode. When the self-gating logic is used during scan shift operations, the stuck-at faults in the self-gating logic can be tested with short test sequences; therefore, the rise in test costs can be mitigated. It is possible to test the stuck-at faults in self-gating logic using only four scan test patterns. The experimental results show that the average of the stuck-at test pattern increase ratio has been dropped from more than 90% to less than 8%. The low-power performance of the proposed method in the mission mode is the same as that of the conventional self-gating structures. When the DSSG method is used, the dynamic power of the shift operation which may increase excessively during the scan test can be reduced. [ABSTRACT FROM AUTHOR]

Automatic test case generation plays a key role in automatic testing for web services. Existing testing techniques based on algebraic specifications rely on the creation，initialization，and replication of objects under test to verify the correctness of test results. However，their third-party nature means that such operations are not usually available，and thus it is hard to support transforming test cases into executable sequences of operations. One possible solution is to convert the test case into a linear execution sequence that contains only one instance o£ the service under test，does not include instance initialization，and only modifies and checks the instance states. We improve the original work and propose to use the test execution graph with inverse terms (TEG-I) to describe state changes during the execution of the test case. We design a TEG-I construction algorithm and a monic execution sequence generation algorithm，and implement prototype tools. A case study demonstrates that the proposal is feasible for automatic test case generation and can improve the testability of web services. [ABSTRACT FROM AUTHOR]

Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit’s data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points—industry-proven design-for-test technology used primarily to enhance the overall design testability–can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation. [ABSTRACT FROM AUTHOR]

Determination of the most appropriate test set is critical for high fault coverage in testing of digital integrated circuits. Among black-box approaches, random testing is popular due to its simplicity and cost effectiveness. An extension to random testing is antirandom that improves fault detection by maximizing the distance of every subsequent test pattern from the set of previously applied test patterns. Antirandom testing uses total Hamming distance and total cartesian distance as distance metrics to maximize diversity in the testing sequence. However, the algorithm for the antirandom test set generation has two major issues. Firstly, there is no selection criteria defined when more than one test pattern candidates have the same maximum total Hamming distance and total cartesian distance. Secondly, determination of total Hamming distance and total Cartesian distance is computational intensive as it is a summation of individual Hamming distances and cartesian distances with all the previously selected test patterns. In this paper, two-dimensional Hamming distance is proposed to address the first issue. A novel concept of horizontal Hamming distance is introduced, which acts as a third criterion for test pattern selection. Fault simulations on ISCAS'85 and ISCAS'89 benchmark circuits have shown that employing horizontal Hamming distance improves the effectiveness of pure antirandom in terms of fault coverage. Additionally, an alternative method for total Hamming distance calculations is proposed to reduce the computational intensity. The proposed method avoids summation of individual Hamming distances by keeping track of number of 0s and 1s applied at each inputs. As a result, up to 90% of the computations are reduced. [ABSTRACT FROM AUTHOR]

This paper presents a novel framework comprises of a Propositional Satisfiability (SAT) encoder and solver. The framework responsible for generating and proving a simplified SAT-based formula of digital circuits for Automatic Test Pattern Generation (ATPG) proposes. The parallel algorithms introduced in this work are aimed at both combinational and sequential circuits and optimized on NVIDIA General-Purpose Graphics Processing Unit (GPGPU) paradigm. The SAT encoder presents an efficient method to apply the Boolean Constraint Propagation (BCP) on-the-fly while the generation is running on the GPU. The simplified formula is further proved for satisfiability using an improved parallel solver on GPU. The proposed encoder executes 93 times faster compared to the sequential counterpart. The test generation algorithm using the GPU-accelerated framework delivers about 5.86 speedup on an average compared to the state-of-the-art Lingeling solver. Moreover, the SAT encoder reduced the run time for fault detection by 6.53 and 11.42% on an average when applied to the proposed and the conventional CUD@SAT solvers, respectively, offering promising related work for the future research. [ABSTRACT FROM AUTHOR]