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Quantization is an effective technique to reduce memory and computational costs for inference of convolutional neural networks (CNNs). However, it has not been clarified which model can achieve higher recognition accuracy with lower memory and computational costs: a fat model (large number of parameters) quantized to an extremely low bit width (e.g., 1 or 2 bits) or a slim model (small number of parameters) quantized to moderately low bit width (e.g., 4 or 5 bits). To answer this question, we define a metric that combines the number of parameters and computations with bit widths of quantized weight parameters. Using this metric, we demonstrate that Pareto-optimal performance, where the best accuracy is obtained at a given memory or computational cost, is achieved when a slim model is moderately quantized rather than when a fat model is extremely quantized. Moreover, employing a strategy based on this finding, we empirically show that the Pareto frontier is improved by 4.3× under a post-training quantization scenario on the ImageNet dataset.

A lot of energy-efficient accelerators for inference has been reported. Our investigation result on dependence of energy efficiency on bit precision of accelerators shows that energy efficiency of in-memory/analog accelerators looks better than that of digital accelerators. However, accuracy of in-memory/analog accelerators is usually deteriorated. In order to practically reduce average bit precision for weights while maintaining accuracy, we introduce our proposed filter-wise quantization technique and a specific HW architecture with variable-bit width MAC units used in a bit-parallel manner. Finally, we discuss whether in-memory/analog accelerators can actually be a silver bullet for energy-efficient inference.

To enhance the efficiency for inference of deep convolutional neural network without noticeable degradation of the recognition accuracy, we have proposed a filter-wise optimized quantization with variable bit precision. In addition, we have proposed the hardware architecture that fully supports the quantized variable bit precision. By using this hardware architecture, the execution time is reduced proportionally to the reduced bit precision by the filter-wise quantization. In the demonstration, we present image classification experiments on an FPGA where the proposed architecture is implemented with less execution time than the fixed 16-bit precision model.

Quantization of models with lower bit precision is a promising method to develop lower-power and smaller-area neural network hardware. However, 4- or lower bit quantization usually requires additional retraining with labeled dataset for backpropagation to improve test accuracy. In this paper, we propose a quantization scheme with distribution-based filter-wise quantization step without labeled dataset. ResNet-50 model with 8-bit activation and 3.04-bit weight precision quantized with the proposed techniques achieves top-1 inference accuracy of 74.3 % on ImageNet.

Many efforts have been made to improve the efficiency for inference of deep convolutional neural network. To achieve further improvement of the efficiency without penalty of accuracy, we propose filter-wise optimized quantization with variable precision and the hardware architecture that fully supports it; as the bit precision for operations is reduced by granulariy optimizing weight bit precision filter-by-filter, the execution time is reduced proportionally to the total number of computations multiplied with the number of weight bit. We implement the proposed architecture on FPGA and demonstrate that ResNet-50 run with 5.3× less execution cycles without penalty of accuracy.

An exponentially Increasing number of wireless-LAN (WLAN) devices In a dense environment causes a decrease in throughput owing to collisions among the devices and the lack of contiguous bandwidth. The next-generation standard of 802.11ax improves spectrum efficiency by additionally supporting 1024 (1K) QAM, OFDMA with 80+80MHz; these impose several challenges to silicon design. 1K-QAM demands extreme IQ balance with an IRR better than −50dB over a wide frequency range up to 80MHz to achieve at least −35dB RX EVM or less. Noise characteristics better than −44dBc LO integrated phase noise as well as 50dB isolation between each TRX chain are mandatory. To best make use of the essential features defined in the 11ax standard, a real-time and arbitrary spectrum-resource control capability at each access point (AP) is beneficial both in terms of further improvement in spectrum efficiency as well as communication reliability in ISM coexisting bands and legacy WLAN. Interference identification of the order of 10μe while incorporating everything into a strictly limited silicon area is key to launching the advanced unique functionality. This paper presents a fully integrated 4×4 802.11abgn/ac/ax-compliant AP transceiver SoC. The chip offers frequency-dependent IQ (FD-IQ) mismatch calibration for both amplitude and phase, low-noise TX BB and multimode LO distribution techniques, and real-time interference detection including 2.4GHz inverter-type microwave (MW) ovens.

Summary. Background: Intron 22 inversion (Inv22) of the coagulation factor (F)VIII gene (F8) is a frequent cause of severe hemophilia A. In addition to Inv22, a variety of F8 mutations (1492 unique mutations) causing hemophilia A have been reported, of which 171 involve deletions of over 50 bp (HAMSTeRs database; http://hadb.org.uk/). However, only 10% of these large deletions have been fully characterized at the nucleotide level. Patients and methods: We investigated gene abnormalities in three unrelated severe hemophilia A patients with high titer FVIII inhibitors. They had previously been shown to carry large deletions of the F8, but the precise gene abnormalities remain to be elucidated. Results: Inverse shifting-PCR (IS-PCR) Inv22 diagnostic tests revealed that these patients carried either type I or II Inv22. However, they showed a wild-type (WT) pattern in the IS-PCR Inv22 complementary tests. We further analyzed their X chromosomes to account for the puzzling results, and found that they had different centromeric breakpoints in the Inv22 X chromosomes, adjacent to the palindromic regions containing int22h-2 or -3, and their spacer region, respectively. The connections appeared to be shifted towards the telomere of the WT F8 Xq28, resulting in a new telomere with an additional intact int22h copy. Conclusions: These gene rearrangements might result from double-strand breaks in the most distal regions of the long arms of the Inv22 X chromosomes, followed by DNA restorations using the WT F8 Xq28 by non-homologous end joining or break-induced replication; thus leading to large F8 deletions in severe hemophilia A patients.

We identified a novel mechanism of hereditary thrombosis associated with antithrombin resistance, with a substitution of arginine for leucine at position 596 (p.Arg596Leu) in the gene encoding prothrombin (called prothrombin Yukuhashi). The mutant prothrombin had moderately lower activity than wild-type prothrombin in clotting assays, but the formation of thrombin-antithrombin complex was substantially impaired. A thrombin-generation assay revealed that the peak activity of the mutant prothrombin was fairly low, but its inactivation was extremely slow in reconstituted plasma. The Leu596 substitution caused a gain-of-function mutation in the prothrombin gene, resulting in resistance to antithrombin and susceptibility to thrombosis.

Hereditary hemorrhagic telangiectasia (HHT) is an inherited autosomal dominant vascular dysplasia caused by mutations in mainly the endoglin gene ( ENG ) or activin-like kinase receptor 1 (ALK1) gene ( ACVRL1 ). We investigated the molecular basis of HHT in a Japanese patient, and identified a novel missense mutation in ENG (c.38T>A, p.Leu13Gln) located in the signal peptide's hydrophobic core, but not in ACVRL1 . In experiments in COS-1 cells, the Leu13Gln (L13Q) mutant endoglin appeared to be expressed as a precursor form, probably due to impaired protein processing. Flow cytometry analyses of the COS-1 cells transiently expressing recombinant endoglins revealed that the wild-type endoglin was detected on the cell surface, but the L13Q mutant was not. We also analyzed expression patterns of the recombinant endoglins by immunofluorescent staining, and found that the wild-type co-localized with the endoplasmic reticulum (ER), but the L13Q mutant did not. These results implied that the L13Q mutant endoglin fails to insert into the ER, probably due to destruction of the hydrophobic core structure in the signal peptide to be recognized by signal recognition particles. Thus, the Leu13 in the signal peptide of endoglin might be essential for correct protein processing through the ER and cell-surface expression. Taken together, the novel c.38T>A mutation in ENG would impair co-translational processing of the endoglin, and could be responsible for HHT in this patient.

A 2.4 GHz 0.13 μm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between ―40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of ―90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 μm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

1.2 V 0.2-to-6.3 GHz transceiver for a multimode radio is fabricated in a 0.13 mum CMOS technology is proposed. The transmitter achieves EVM of less than -29.5 dB at -3 dBm output from 0.2 to 7.2 GHz while consuming 69 mW, where the modulation scheme used is equivalent to 802.11a, 54Mb/s mode. Without any explicit matching components, S22 and S11 are kept less than -9.5 dB and -9.2 dB, respectively, over the frequency range from 0.1 to 6.3 GHz. To achieve wideband output matching, a parallel combination of a common-source amplifier and a source-follower buffer is used. This structure copes with both 50 Omega output resistance, and small output capacitance. The choke in the pre-power-amplifier (PPA) is also eliminated by adopting a push-pull amplifier and by using a modified envelope signal injection biasing scheme. The PPA achieves OP 1dB of 6 dBm, which corresponds to almost the rail-to- rail swing for 1.2 V power supply.

A 5 GHz MIMO direct-conversion transceiver composed of 2 transmitters (TXs) and 3 receivers (RXs) is fabricated with 0.13 mum CMOS technology. Die size is 4.56 mm times 7.7 mm. For driving 10 GHz LO signal lines of 5 mm length for both TXs and RXs, inductor-less low-power LO repeaters are equipped in individual LO paths. A linearized RF variable gain amplifier is proposed for low power operation. Isolation of over 40 dB is obtained by equipping separate GNDs on both the MIMO IC and the circuit board. This results in negligible degradation of EVM. TX EVM of over -31 dB is obtained at -8.6 dBm for 2 TX mode when external LO of 10 GHz is applied. The 3 RXs and 2 TXs with LO paths dissipate 703 mW and 412 mW from 1.5 V, respectively.