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Introduction: Type 2 Diabetes Mellitus (DM2) viewed as a major cause for neurodegenerative and cognitive abnormalities. One of the possible reason for that should be insulin resistance and hyperinsulinemia two main clinical future of DM2. The mechanism relationship between insulin and development of diabetic neuropathy and encephalopathy not clear yet. Material and methods: In 51 DM2 patients in age between 42 and 64 years old, without neurologic complications or with presence of different stages of neuropathy/encephalopathy were observed clinically and diagnosis confirmed by neurologist. Patients divided into two groups according to presence of mild and severe neuropathy or encephalopathy. For lab study cubital venous blood plasma taken for measure of plasma insulin level by ELISA. Results: Neuropathy/encephalopathy were registered in 71% of DM2 patients. HbA1c level were higher than healthy subjects and were comparable in both groups with severe neuropathy/encephalopathy and without. Blood plasma insulin level were between 14 and 21,7 μU/ml, significantly higher than normal ranges (0,7 – 9,07 μU/ml). Plasma insulin level were decreased according to severity of neuropathy/encephalopathy, and suggested about linkage between functional activity of beta-cells and neurodegeneration. Index HOMA-B indicates decreasing of beta-cells functional activity. Index Caro (glucose to insulin ratio) also been decreased and suggested about insulin resistance in these patients. When we analysed blood plasma insulin level according to presence and severity of diabetic neuropathy and encephalopathy there was significant Conclusion: Neurodegeneration is a frequent future of DM2 and were found in 71% cases. Presence and severity of neurodegeneration in DM2 have negative linkage with plasma insulin level and suggest about involvement of insulin resistance into pathogenesis of neurodegeneration. no funding or grants This is the full abstract presented at the American Physiology Summit 2023 meeting and is only available in HTML format. There are no additional versions or additional content available for this abstract. Physiology was not involved in the peer review process.

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.

In this paper, we present a current transport model of MoS2-based dual gate tunnel field effect transistor from both analytical and numerical techniques. In analytical modeling, two-dimensional (2D) model of potential distribution with its corresponding energy level for the hetero-junction has been solved and implemented with Landauer current transport mechanism. The output characteristics have been compared with the quantum mechanical solution obtained from non-equilibrium Green's function (NEGF) formalism. The sub-threshold slope (SS), obtained from analytical and NEGF methods are 10 mV/decade and 12.6 mV/decade with on/off current ratio of 107 and 106, respectively at VDS = 0.5 V. We have considered scattering mechanism into our calculation and have shown that carrier transportation for 20 nm channel length is diffusive. In addition, scattering reduces the on current by an order of magnitude, and resembles good agreement with the atomistic simulation. Lastly, mobility and ionized impurity concentration for our proposed structure have been calculated as 27.2 cm2/Vs and 1.17 × 1013/cm2.

This work examines the design of high Q-factor inductor for LC voltage-controlled oscillator (VCO) in TSMC 0.18μm n-well CMOS process technology and 1.5 V supply voltage. The planar structure of graphene and its sufficient relation time make it easier to pattern graphene into helical structures without additional contacts at each corner. The inductor is modelled with the widely accepted π-mudel and the results show that graphene inductor achieves a high Q-factor with reduced parasitics and losses when compared with Cu wire inductor. Following this, we employed the inductor in the design of 2 GHz LC VCO. From the Cadence/Spectre simulations, we obtained that the tuning range of voltage-controlled oscillator is 1.62 GHz to 3.93 GHz and the phase noise measured is -124.8 dBc/Hz at 1 MHz offset frequency. In addition, the VCO has a figure of merit (FoM) of206.4 dBc/Hz and consumes 3.66 mW power.

Stable room temperature operation of field-effect transistor (FET) based on two-dimensional silicon (silicene) has recently been reported. Like graphene, silicene is a Dirac cone material. Silicene-based devices provide high off-state leakage current due to lack of a significant bandgap. However, quantum confined silicene nanoribbon (SiNR) shows observable bandgap which can be used for making switching transistors for digital integrated circuit design. Contrary to metal oxide semiconductor FET (MOSFET), tunnel field-effect transistor (TFET) overcomes the physical limit of scaling of supply voltage. In this work, we present structure and characteristics of SiNR TFET using atomistic simulation based on self-consistent solution of 3D Poisson and Schrodinger equations within the non-equilibrium Green’s function formalism. Performances are also compared with the International Technology Roadmap for Semiconductors projected high performance requirements of 2026 nMOSFETs.

Multiple-input floating gate MOSFET also known as a neuron MOSFET or neural transistor and floating gate potential diagrams have been used for the conversion of ternary-valued input into corresponding binary output in CMOS integrated circuit design environments. The method is demonstrated through the design of a circuit for conversion of ternary inputs 00 to − 1− 1 (decimal 0 to − 4) and 00 to 11 (decimal 0 to + 4) into the corresponding binary bits in a standard 0.5 μm digital CMOS technology. The physical design of the circuit is simulated and tested with SPICE using MOSIS BSIM3 model parameters. The maximum propagation delay of the output is nearly 1.2 μs. The conversion method is simple and compatible with the present CMOS process. The circuit could be embedded in digital CMOS VLSI design architectures.

We present an analog-integrated circuit implementation of long short-term memory network, which is compatible with digital CMOS technology. We have used multiple-input floating gate MOSFETs as both the front-end to obtain converted analog signals and the differential pairs in proposed analog multipliers. Analog crossbar is built by the analog multiplier processing matrix and bitwise multiplications. We have shown that using current signals as internal transmission signals can largely reduce computation delay, compared to the digital implementation. We also have introduced analog blocks to work as activation functions for the algorithm. In the back-end of our design, we have used current comparators to achieve the output to be readable to external digital systems. We have designed the LSTM network with the matrix size of 16 × 16 in TSMC 180nm CMOS technology. The post-layout simulations show that the latency of one computing cycle is 1.19ns without memory, and power dissipation of the single analog LSTM computing core with 2 kilobytes SRAM at 200MHz is 460.3mW. The overhead of power dissipation due to SRAM access is 8.3%, in which the computing of each LSTM layer requires one computing cycle. The energy efficiency is 0.95TOP/s/W.

With the steady advancement of human civilization, energy lack and ecological contamination have become an ever-increasing number of critical difficulties in our reality, and they are issues that should be settled desperately. Perovskite, a potential material for sustainable ideal energy source, boundless, and clean energy. Perovskite with general formula ABX3 plays an important role in electrode and electrolyte for solar cells which is most ideal alternatives to silicon solar cells, supercapacitor, Bio fuel and solid oxide fuel etc. because of their stability, ferroelectric, supreme, catalytic, dielectric and high charge carrier mobility. In this paper the perovskite doped with rare earth Gd and Nd was synthesise by a solid reaction technique at high temperature. XRD confirms the tetragonal structure of single step. Dielectric behaviour of PVSK ceramics was studied using CIS technique within range of 9000C to 12500C and frequency range of 1 kHz and 1 MHz the existence of the ac conductivity variance indicates the electrical conductivity form of Arrhenius. The dielectric constant of the materials is very high which is needed for the energy storage device. The material's tangent loss is very low until the transition temperature is very high. The tolerance factor of PVSK material was found to be nearly 1.

This work presents the implementation of analytical transport model of M o S 2 tunnel field effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model are extracted, and most notable is its high I ON /I OFF ratio, which makes it suitable for low power design, and IoT applications. Subsequently, we employ the TFET model in the design of ultralow power phase locked loop (PLL). Various components of PLL are examined in terms of their structures and functions. The results show that the voltage controlled oscillator (VCO) operates from 0.5 GHz to 2.9 GHz with a tuning range of 82.8%. It also consumes 1.91 μW power at 2 GHz carrier and has a phase noise of -117.3 dBc/Hz at 1 MHz offset frequency. The average power consumed by phase locked loop is 0.021 mW. In addition, the operation of the PLL is not sensitive to temperature variations.

Molybdenum disulfide (MoS2) is a two-dimensional material which has demonstrated semiconducting behavior [1]. Different kinds of irradiations create the defects in molybdenum disulfide (MoS2) structure, different types of irradiations modulate the density of sulfur vacancies in MoS2[1]. MoS2 based and other 2-D materials-based devices and sensors are used in harsh environments [1]. In [2] authors have demonstrated studies of gamma irradiation on mono layer graphene. To develop and fabricate the MoS2-based devices and sensors, nanoelectronics instrumentation such as Transmission Electron Spectroscopy (TEM), Scanning Electron Microscopy (SEM), Raman Spectroscopy, X-ray Photo-Electron Diffraction (XPS) techniques are required for characterization of MoS2. Moreover, these radiation techniques, have huge impacts on electronic and optical properties of MoS2 [3]. So, it is important to study irradiation effects on the crystal structure and properties of MoS2. In this work, Co-60 source was used for the irradiation, which has nominal irradiation dose 2.07 Gy/min (207 rad/Min) (±5%). We have irradiated gamma-rays on four samples of single-layer molybdenum disulfide over copper substrate. We exposed the irradiation dose of 1.0 kGy (100 krad), 1.75 kGy (175 krad), 2.65 kGy (265 krad) and 3.0 kGy (300 krad) of irradiations on sample number one, two, three and four respectively. Through the Raman Spectroscopy, we studied E12g, A1g peaks. A1g peak is at 403.6 cm-1 and E12g peak is at 384.7 cm-1 in pristine MoS2 Raman spectroscopy. Raman spectroscopy is nondestructive tool for characterization of S vacancies in MoS2.

In this chapter, we have shown how to use DFT for modelling material and finding their electronic structure. We have shown how to calculate the band diagram and expanded it to the calculation of transport. Hybrid material modelling has been shown in the context of VLSI interconnect. We also described the calculation methods for quantum capacitance of a hybrid G/Cu nanoribbon using DFT. Although in this chapter we have shown up to transport calculation and capacitance properties, DFT can be implemented to calculate other relevant properties of the material. This calculation methodology will help finding transport properties and quantum capacitance of emerging materials. The chapter can be a good starting point in advancing an understanding of electrical performances of other nanostructures for possible interconnect and device materials.

In this chapter, an analytical current transport model of a p-i-n n-type armchair GNR TFET is developed which is compared with numerical simulation. Two separate current transport models are derived analytically from semi-classical and semi-quantum modeling approaches. Non-equilibrium Green function (NEGF)-based numerical simulation study is also carried out. Results obtained from these two methods are compared with the numerical simulation to establish analytical models. The analytical model in the work of Zhang et al. [2] is revisited and results are also compared with the analytical and numerically simulated results in this work. Furthermore, GNR TFET's performance is studied for varying GNR width using semi-classical, semi-quantum and NEGF simulation-based current transport models. Finally, complementary GNR TFET inverter for digital circuit design is demonstrated through the computation of voltage transfer characteristic from all three modeling approaches.

A new type of graphene-switching transistor termed as "junctionless tunnel effect transistor (JTET)" based on graphene-hBN-graphene vertical heterostructure and interlayer tunneling is proposed and an analytical current transport model has been developed. The drain current in graphene JTET flows between the source and drain of bottom graphene layer. The current in the channel is regulated by the shift in channel Fermi level which depends on the net vertical tunneling of carriers from top graphene to bottom graphene layers through hBN. Performance of graphene JTET is evaluated for different numbers of hBN layers. A comparison between graphene JTET and ITRS projected 2020 nMOSFET is also provided apart from graphene JTET performance comparison with similar iTFETs. Current saturation is observed in graphene JTET output characteristic for both p- and n -type operations, which makes graphene JTET suitable for digital circuit design. Graphene JTET is also capable of suppressing NDR effect, and shows steep subthreshold slope with high on/off current ratio and normal operation at room temperature. A complementary vertical inverter is presented similar to a CMOS inverter and analyzed for its performance. Graphene JTET vertical inverter gives inverter gain higher than unity at the low supply voltage and both low and high noise margins. It is concluded that with an average 25 mV/decade subthreshold slope at 0.1 V supply voltage and a current ratio of ~104 , graphene interlayer junctionless tunnel effect transistor meets the ITRS requirement of device scaling for energy-efficient circuit design.

Graphene with its unique electronic properties is highly suitable for numerous electronic applications. Among different growth techniques, CVD is most promising due to its low cost and large area. However, growth of large-area single crystal graphene is still challenging. Owing to its zero bandgap property, graphene is not yet suitable for digital applications. However, finite bandgap can be obtained in the form of GNR which demonstrates width and edge-type dependent energy bandgap. GNR TFET can be a viable option for low power high-performance integrated circuit design. By utilizing the zero band properties of graphene, the promise of graphene interlayer tunnel transistor can also be explored. Other than graphene 2D materials such as layered transition-metal dichalcogenide (TMD) and Xenes have emerged and shown great promise for electronics, photonics, energy harvesting, and biosensors.

In this chapter, the operating principle of JTET discussed in Chapter 11 has been extended for the study of MoS2 JTET considering MoS2 /hBN/MoS2 for reduced subthreshold slope operation and sustainable leakage. The interlayer tunneling-based barrier control mechanism as proposed for graphene JTET in Chapter 11 and [16] is used for the current transport study of MoS2 JTET through self-consistent simulation method [22]. Similar to graphene JTET, multilayer hBN is considered as the gate dielectric for MoS2 JTET. The performances of MoS2 JTET are compared with the earlier reported graphene-based iTFET.

Graphene is a two-dimensional material and has demonstrated an exceptional electronic and photonic properties for unlimited applications including its use in extreme environments of the space. There are several known techniques of formation of graphene onto different types of substrates such as the substrate transfer process and direct deposition. In this work, we deposited monolayer graphene over copper and nickel substrates in NanoCVD-8G Graphene reactor using argon plasma, and methane as a carbon source and studied effects of gamma irradiation using Cobalt-60 source. Radiation effects on crystalline structure of graphene is examined using Raman Spectroscopy and X-ray Photo Electron Spectroscopy (XPS). In our experiment, we used irradiation dose from 1 kGy to 2.65 kGy for different samples of graphene over copper and nickel substrates. For the graphene grown on the nickel substrates, we exposed the irradiation dose of 1.0 kGy and 2.5 kGy on two samples, respectively. For the graphene grown on the copper substrates, we exposed 1.25 kGy, 1.75 kGy, and 2.65 kGy irradiation dose on three samples, respectively. We observed D-peak in graphene deposited over nickel and copper substrates caused by disordered structure of graphene after Co-60 exposure. After the Raman spectroscopy and XPS studies, same amount of irradiation was used for second set of irradiation dose experiment. XPS data on Co-60 exposed samples showed four peaks positioned at 284.8eV, 285.3eV, 286.0 eV and 288.5 eV for C-C, C-OH, C-O-C and COOH bonds, respectively. Analysis of the results shows weakening of C-C bonds and formation of C-OH, C-O-C and COOH bonds implying reduced electrical conductivity of graphene.

Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.