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1. DESIGN AND SIMULATION OF A 10 GSPS LOW POWER SAMPLE AND HOLD LESS ANALOG TO DIGITAL CONVERTER USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS

Author

Satish S. Narkhede and Aonkar B Takalikar

Subjects
Computer science, lcsh:TK7800-8360, Analog-to-digital converter, 02 engineering and technology, 01 natural sciences, law.invention, adc, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 010302 applied physics, business.industry, lcsh:Electronics, Electrical engineering, Sample and hold, pipelined, 020202 computer hardware & architecture, Power (physics), Bit (horse), Effective number of bits, cnfet, Field-effect transistor, gsps, Nyquist frequency, business, Voltage
Abstract

A 5 bit sample-and-hold less pipelined ADC is presented for high speed and low power applications. The architecture is designed using 32nm CNFET model in Hspice and simulation is carried out at 10 GSPS sampling rate. From the simulation results, the SNDR is found out to be 32.89dB at Nyquist frequency and the ERBW is found to be 3GHz from 2 to 5GHz in which ENOB is guaranteed to be above 4.6. The average power consumed is 5.031mW for a supply voltage of 1.4V and FoM is 53.32fJ/step.

Published
2017
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