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Thermal capacitances are required to describe the fast dynamic thermal behavior in the silicon-on-insulator (SOI) devices. This article presents a physical model based on the ac technique, together with the characteristic thermal frequency determination through the frequency response of the output conductance, for calculating the thermal capacitance of single-finger and multi-finger SOI-MOSFETs. The model accounts for the total gate width and substrate temperature, making evident the augmented thermal coupling when multi-fingers are used. The thermal capacitances and the corresponding time constants, extracted from a variety of gate widths and number of fingers, are correctly predicted up to a substrate temperature of 150 °C. This work was supported by the Spanish MEC under Project GREENSENSE−TEC2015-67883-R and RTI2018-096019-B-C31

Background and Purpose— Many patients with acute ischemic stroke are not eligible for thrombolysis or mechanical reperfusion therapies due to contraindications, inaccessible vascular occlusions, late presentation, or large infarct core. Sphenopalatine ganglion (SPG) stimulation to enhance collateral flow and stabilize the blood-brain barrier offers an alternative, potentially more widely deliverable, therapy. Methods— In a randomized, sham-controlled, double-masked trial at 41 centers in 7 countries, patients with anterior circulation ischemic stroke not treated with reperfusion therapies within 24 hours of onset were randomly allocated to active SPG stimulation or sham control. The primary efficacy outcome was improvement beyond expectations on the modified Rankin Scale of global disability at 90 days (sliding dichotomy), assessed in the modified intention-to-treat population. The initial planned sample size was 660 patients, but the trial was stopped early when technical improvements in device placement occurred, so that analysis of accumulated experience could be conducted to inform a successor trial. Results— Among 303 enrolled patients, 253 received at least one active SPG or sham stimulation, constituting the modified intention-to-treat population (153 SPG stimulation and 100 sham control). Age was median 73 years (interquartile range, 64–79), 52.6% were female, deficit severity on the National Institutes of Health Stroke Scale was median 11 (interquartile range, 9–15), and time from last known well median 18.6 hours (interquartile range, 14.5–22.5). For the primary outcome, improved 3-month disability beyond expectations, rates in the SPG versus sham treatment groups were 49.7% versus 40.0%; odds ratio, 1.48 (95% CI, 0.89–2.47); P =0.13. A significant treatment interaction with stroke location (cortical versus noncortical) was noted, P =0.04. In the 87 patients with confirmed cortical involvement, rates of improvement beyond expectations were 50.0% versus 27.0%; odds ratio, 2.70 (95% CI, 1.08–6.73); P =0.03. Similar response patterns were observed for all prespecified secondary efficacy outcomes. No differences in mortality or serious adverse event safety end points were observed. Conclusions— SPG stimulation within 24 hours of onset is safe in acute ischemic stroke. SPG stimulation was not shown to statistically significantly improve 3-month disability above expectations, though favorable outcomes were nominally higher with SPG stimulation. Beneficial effects may distinctively be conferred in patients with confirmed cortical involvement. The results of this study need to be confirmed in a larger pivotal study. Clinical Trial Registration— URL: https://www.clinicaltrials.gov . Unique identifier: NCT03767192.

In this article, pulsed measurements of thermal resistance in GaN-based high-electron mobility transistors (HEMTs) on silicon, with different gate geometries and gate-to-drain extensions, are analyzed and modeled. Simple expressions for the thermal resistance of silicon-on-insulator (SOI) MOSFETs, which take into account the gate width and channel length, can be adapted to model the thermal resistance of these GaN-based HEMTs. Narrow width effects and the increase in the heat flow through the gate as the channel length increases were correctly reproduced. In addition, numerical simulations were performed to explain the reduction obtained in thermal resistance as the gate-to-drain extension increases. Our approach can also be applied easily to other well-established models using circuit simulators.

Virtual platforms provide a full hardware/software platform to study device limitations in an early stages of the design flow and to develop software without requiring a physical implementation. This paper describes the development process of a virtual platform for Deep Packet Inspection (DPI) hardware accelerators by using Transaction Level Modeling (TLM). We propose two DPI architectures oriented to System-on-Chip FPGA. The first architecture, CPU-DMA based architecture, is a hybrid CPU/FPGA where the packets are filtered in the software domain. The second architecture, Hardware-IP based architecture, is mainly implemented in the hardware domain. We have created two virtual platforms and performed the simulation, the debugging and the analysis of the hardware/software features, in order to compare results for both architectures.

DC characteristics of AlGaN/GaN on Si single finger MOS-HEMTs, for different gate geometries, have been measured and numerically simulated with substrate temperatures up to 150 °C. Defect density, depending on gate width, and thermal resistance, depending additionally on temperature, are extracted from transfer characteristics displacement and the AC output conductance method, respectively, and modeled for numerical simulations with Atlas. The thermal conductivity degradation in thin films is also included for accurate simulation of the heating response. With an appropriate methodology, the internal model parameters for temperature dependencies have been established. The numerical simulations show a relative error lower than 4.6% overall, for drain current and channel temperature behavior, and account for the measured device temperature decrease with the channel length increase as well as with the channel width reduction, for a set bias.

Different causes of the gate leakage origin in AlGaN/GaN HEMTs on Si have been studied through numerical simulations. Based on DC measured results and employing Sentaurus Device, different trap effects under the Schottky gate must be included to reproduce the measured transfer characteristics in subthreshold regime. Additionally, numerical simulation aspects for GaN-based HEMTs are also detailed.

In this paper, DC characteristics of an AlGaN/GaN on sapphire high-electron mobility transistor (HEMT) are measured, numerically simulated, and modelled accounting for self-heating effects (SHEs), with the main electrical parameters being extracted. Decomposing the transistor thermal resistance into the buffer and substrate components, our study can be easily extended to other substrate materials. Thus, sapphire is substituted with silicon, molybdenum, and SiC, which reduce current-collapse due to SHEs thanks to their considerably higher thermal conductivity, which improves transistor performance. Furthermore, we implement a compact model available for AlGaN/GaN HEMTs, incorporating the temperature dependence of extrinsic source/drain ohmic resistances, which are numerically evaluated for the different substrates.

This paper describes the work done to design a SoC platform for real-time on-line pattern search in TCP packets for Deep Packet Inspection (DPI) applications. The platform is based on a Xilinx Zynq programmable SoC and includes an accelerator that implements a pattern search engine that extends the original Boyer-Moore algorithm with timing and logical rules, that produces a very complex set of rules. Also, the platform implements different modes of operation, including SIMD and MISD parallelism, which can be configured on-line. The platform is scalable depending of the analysis requirement up to 8 Gbps. High-Level synthesis and platform based design methodologies have been used to reduce the time to market of the completed system.

DC characteristics of AlGaN/GaN on Si MOS-HEMTs are measured and numerically simulated, with substrate temperature up to 140°C, varying the gate width and gate length. Different gate recess depths are simulated in ATLAS in order to further investigate and optimize the device performance. Thermal boundary conditions and device thermal resistance are included in the structure for accurate simulation of the heating response. In addition, the relationship of the threshold voltage and saturation velocity with the substrate temperature and gate width has been studied and set in order to ease the modelling of these devices.

Availability of hardware implementations of super-resolution image reconstruction algorithms is limited mostly by their logical and memory requirements. This is also the case for other image processing algorithms such as hyperspectral, image compression, image coding, video coding. In previous publications we have introduced a new execution flow that tackles the problem of high memory requirements of a restoration-interpolation super-resolution kernel by carrying out processing in a macroblock-by-macroblock manner. In this work we present the modelling framework used for the evaluation of the proposed execution flow. The modelling process is presented in a step-by-step manner by means of a real-life example of implementation of super-resolution image reconstruction with description of the choices made at every stage and explanation of the reasoning behind. In the presented case the use of the proposed frame-work led to a hardware implementation with real-time capabilities. This frame-work can be applied to similar algorithms, helping system designers in achieving better work organization and efficiency.

Nowadays, most of the image contents are recorded in high resolution (HR). Nevertheless, there is still a need of low resolution (LR) content presentation when recapturing is unviable. As high resolution content becomes commonplace (with HDTV penetration in US estimated at 65% for 2010) the viewers expectations on quality and presentation become higher and higher. Thus, in order to meet today?s consumer expectations the LR content quality has to be enhanced before being displayed. Content pre-processing/upscaling methods include interpolation and Super-Resolution Image Reconstruction (SRIR). SRIR hardware implementations are scarce, mainly due to high memory and performance requirements. This is the challenge we address. In this work an efficient super-resolution core implementation with high quality of the super-resolved outcome is presented. In order to provide high outcome quality the implementation is based on state-of-the-art software. The software algorithm is presented and its output quality compared with other state-of-the-art solutions. The results of the comparison show that the software provides superior output quality. When implemented in targeted FPGA device, the system operating frequency was estimated at 109 MHz. This resulted in a performance that allows dynamic 2x super resolution of QCIF YUV 4:2:0p sequences at a frame rate of 25 fps, leading to realtime execution using only on-chip device memory. Post-layout simulations with back-annotated time proved that the hardware implementation is capable of producing the same output quality as the base software.

AlGaN/GaN HEMTs with sapphire substrate have been measured and numerically simulated considering self-heating effects. A complete DC performance was realized to extract the main electrical parameters with the aim to obtain a proper characterization of the sample. Afterwards, an accuracy and simple methodology has been established to determine the device thermal resistance with other possible substrates, Si, SiC and Mo, which are more suitable due to their lower thermal conductivity. Finally, we modify a compact model for AlGaN/GaN transistors to include the extrinsic resistances obtained from numerical simulations with all substrates.

In this paper, DC characteristics of an AlGaN/GaN on sapphire high-electron mobility transistor (HEMT) are measured, numerically simulated, and modelled accounting for self-heating effects (SHEs), with the main electrical parameters being extracted. Decomposing the transistor thermal resistance into the buffer and substrate components, our study can be easily extended to other substrate materials. Thus, sapphire is substituted with silicon, molybdenum, and SiC, which reduce current-collapse due to SHEs thanks to their considerably higher thermal conductivity, which improves transistor performance. Furthermore, we implement a compact model available for AlGaN/GaN HEMTs, incorporating the temperature dependence of extrinsic source/drain ohmic resistances, which are numerically evaluated for the different substrates. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

In this work, the factors of reduction of memory requirements and increase in memory traffic associated with the change from reference frame level (baseline algorithm) to macroblock-level for the Super-Resolution (SR) image restoration non-uniform grid projection algorithm are compared over combinations of algorithm parameter values. Then, based on the results of a study on the share of algorithm steps code in the total requirements, the code with larger room for optimization has been identified and optimized. The introduction of a new addressing scheme that takes advantage of the algorithms static characteristics have led to a state in which for 87 out of 96 tested combinations (QCIF frame format) the factor of memory occupancy reduction is greater than the factor of increase in memory trafile. This result opens a way for efficient hardware implementations.

This work analyses the dc response of InGaAs channel modulation-doped field-effect transistors, when varying temperature from 300 to 400 K. An analytical model for the intrinsic drain current is derived from previous work, carried out for a similar AlGaAs channel device, in order to show explicitly the temperature dependence. The extrinsic resistances are numerically evaluated and added in a straightforward form to the model. Experimental output characteristics at different temperatures of an InGaAs MODFET, in static operation, are compared with those offered by the resulting extrinsic model and numerical simulations. Computed relative errors are around 10%.

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a single-chip multi-processor for real-time (networked) embedded systems is the multi-microprocessor (MµP). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper, we explore the main design issues of the architecture platform on which the MµP is based. In addition, synthesis results are presented for a lightweight configuration of this architecture platform.

In this work we propose a modification to the conventional lumped equivalent circuit model for integrated inductors. Also the widely used parametric model is modified. The proposed models expand the frequency range where the integrated inductor behavior is accurately predicted. They are useful in developing automatic tools to assist the designers in selecting and automatically laying-out integrated inductors l1r. This work is based on measurements from integrated inductors fabricated in a standard silicon process.

The drain current in a pseudomorphic heterostructure FET (P-HFET) has a negative temperature dependence which is correctly predicted when the electron transport through the barriers is taken into account. In order to compare simulation with experimental results, the static output characteristics on a long gate P-HFET have been measured over the temperature range 260–380 K. Hall mobility measurements at different temperatures and gate bias are included in the simulations. The static characteristics are simulated using a thermionic field emission model that calculates the current across the Al0.3Ga0.7As/In0.3Ga0.7As heterojunction, where the effective band discontinuity is controlled by means of a parameter called effective length, lef. In this paper the use of lef as a fitting parameter for the static characteristic curves is investigated.

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.