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National audience; Nous avons développé un système de sécurité ultime (USD) capable de répondre en quelques millisecondes à une intrusion sur un système en venant physiquement détruire les données avant toutes altérations, vole ou revers engineering. Pour ce faire nous avons dans un premier temps élaboré notre Matériau Energétique (ME) à base de nanothermite Al/CuO et complexe de cuivre et mélangé à du polymère, PVP, pour le stockage en solution et sa dépose par direct writing. Avec 450 mg de matériau stocké dans un boitier muni d’un initiateur, capable de s’initier en quelques dizaines de μs, nous sommes capables de détruire de manière irréversible un composant sensible.

International audience; We developed an Ultimate Security Device (USD) that can, in case of intrusion or external attack, blow up a safetycritical component such as memory device. The device consists of two active parts (1) a pyroMEMS ignites in a fraction of millisecond (2) a mass of reactive composite, both encapsulated into a printed hermetic cap and placed over the sensitive component to be protected. After the presentation of the design and integration of the USD, we demonstrated that 400 mg of reactive composite permits to irreversibly destroy the silicon chips (~118 mm 3) in less than 10 ms. This ultimate security device provides a speedy and automatic response and can be programmed for tunable actions (generation of pressure burst, heat, chemical species) to implement relevant emergency safety responses.

The certMILS project (http://www.certmils.eu/) aims at easing building and certification of complex critical systems by using a certain architecture for structuring these systems into partitions that run on a separation kernel, called MILS (Multiple Independent Levels of Security / Safety). Once a critical system is structured by use of a separation kernel, then this technical structuring should lend itself also to a similarly logically structured security and safety argument in certification. Analogous to the separation kernel that is to be used for building a MILS system, this deliverable provides a security architecture template that is to be used for the certification of that MILS system. The target audience of this document is: * Developers of systems,based on a MILS architecture, providing them a template about how to describe their MILS system. * Security evaluators of a MILS-based system, giving hints about how the developer description can be used to argue for compliance to Common Criteria (CC) and IEC 62443. The assurance case made by the security architecture template in this document identifies as building blocks the security mechanisms implemented by a MILS separation kernel and a typical application payload in partitions and derives typical security architecture arguments for MILS-based systems.

Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First, offshore chip manufacturing allows the design secrets of the IP cores to be transparent to the foundry and other entities along the production chain. Second, small malicious modifications to the design may not be detectable after fabrication without anti-tamper mechanisms. Counterfeit Integrated Circuits (ICs) also have become an important security issue in recent years, in which counterfeit ICs that perform incorrectly or sub-par to the expected can lead to catastrophic consequences in safety and/or mission-critical applications, in addition to the tremendous economic toll they incur to the semiconductor industry. Some techniques have been developed in the past to improve the defense against such attacks but they tend to fall prey to the increasing power of the attacker. We present a new way to protect against tampering by a clever obfuscation of the design, which can be unlocked with a specific, dynamic path traversal. Hence, the functional mode of the controller is hidden with the help of obfuscated states, and the functional mode is made operational only on the formation of a specific interlocked Code-Word during state transition. A novel time-stamp is proposed that can provide the date at which the IC was manufactured for counterfeit detection. Furthermore, we propose a second layer of tamper resistance to the time-stamp circuit to make it even more difficult to modify. Results show that methods proposed offer higher levels of security with small area overhead. A side benefit is that any small alteration will be magnified via the obfuscated design proposed in these methods. Master of Science