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This paper proposes a control system for a quadratic boost DC/DC converter in a wide range of operations, based on an inner loop with a sliding mode controller, for reaching a desired equilibrium state, and an outer loop with integral-type controller, for assuring robustness against load and input voltage variations and converter parameter uncertainties. The sliding mode controller is designed with the extended linearization method and assures local asymptotic stability, whereas the integral controller is designed using classical frequency methods, and assures input–output stability. It is shown that the proposed controller also deals with the sudden changes in the nominal operating conditions; thus, if a change of the operating conditions takes place, the proposed control scheme automatically creates a sliding regime which stabilizes the converter trajectories to the new equilibrium point. Experimental results carried out on a suitably developed test set up show the effectiveness of the proposed approach.

In recent years, new efficient power devices have been implemented. Silicon Carbide has replaced silicon as regards the production and the utilization of many devices, such as MOSFETs, diodes, IGBTs and many others. SiC devices are characterized by a low reverse recovery charge, high carrier saturation velocity, by which it is possible to work at high frequency, and high breakdown voltage. Thanks to the great thermal conductivity and the wide bandgap, these devices can operate at high temperature and reach high voltages and currents. What is important to stress is the fact that power losses in SiC devices are lower than the silicon ones. These are the reasons why these devices are utilized in a wide range of technological applications, including power electronics. In this paper, power losses in Si and SiC devices are evaluated in simulation and compared to each other. In order to demonstrate the remarkable advantages of the SiC devices over the silicon ones, a study which makes use of an isolated DC-DC converter has been conducted. As regards the proposed full-bridge converter, SiC and silicon MOSFETs and diodes, of whom some static and dynamic parameters are defined, are used in order to transfer power from a DC voltage supply to a load.

Nowadays, solder reliability in new power electronic packages is an important research topic. Therefore, it is of paramount importance to properly understand and model the material behaviour and to develop a calculation model to predict reliability performances. This work presents a thermo-mechanical analysis of different solder layers for a low voltage discrete package. The solder joint reliability between package and PCB is also considered in the simulation. This modelling activity is possible by employing the Anand visco-plastic model and by means of a finite element model implemented in COMSOL. The number of cycles to failure can be subsequently computed, with the Darveaux method, for fatigue life estimation purpose.

Power SiC MOSFETs are going to substitute Si devices by to their significantly better performances that make them much suitable in power switching applications such as electric/hybrid vehicles. The increasingly use of these devices in critical mission profiles requires an ever-higher reliability, whereas the increase of the dissipated power during high-speed working cycling due to short current pulses leads to unavoidable thermal and mechanical stress. Here, we propose a direct method to evaluate the mechanical stress due to current pulses. This method highlights that high Power SiC-based MOSFET undergoes to almost two different thermomechanical processes with completely different time scale. The results allow a link between the thermo-mechanical stress and the device failure conditions, with special focus on the current pulses effects on metal surface, as this is a main power devices weakness.

In this work the warpage of a power modules ceramic substrates due to temperature variation has been numerically calculated. It has been used a not linear finite element model, which account the experimentally characterized material properties, including the copper elastoplasticity. Model results have been compared with dedicated interferometric measurements to validate the model. As application example, it has been calculated the benefit in terms of temperature warpage realized with a different substrate design option.

In this paper, SiO2 layers deposited on 4H-SiC and subjected to different post deposition annealing (PDA) in NO and N2O were studied to identify the key factors influencing the channel mobility and threshold voltage stability in 4H-SiC MOSFETs. In particular, PDA in NO gave a higher channel mobility (55 cm2V-1s-1) than PDA in N2O (20 cm2V-1s-1), and the subthreshold behavior of the devices confirmed a lower total amount of interface states for the NO case. This latter could be also deduced from the behavior of the capacitance-voltage characteristics of 4H-SiC MOSFETs measured in gate controlled diode configuration. On the other hand, cyclic gate bias stress measurements allowed to separate the contributions of interface states (Nit) both on the upper and bottom parts of the 4H-SiC band gap and near interface oxide traps (NIOTs) in the two oxides. In particular, it was found that NO annealing reduced the total density of charges trapped at the interface states down to 3 x 1011 cm- 2 and those trapped inside the oxide down to 1 x 1011 cm-2. Electron energy loss spectroscopy demonstrated that the reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide (~ 1nm) and carbon-related defects (< 1nm) at the interface, respectively. This correlation represents a further step in the comprehension of the physics of the SiO2/4H-SiC interface explaining the mobility and threshold voltage behavior of 4H-SiC MOSFETs.

This work has investigated the impact of crystallographic structure on SnAgCu (SAC) solder reliability at print board circuit (PCB) level. A detailed reliability analysis has been performed on packages with different solder thickness. The correlation between experiments and Finite Element Model results explains how NiAu metallization and the reduction of solder thickness improve the solder joint reliability performances.

In recent years, the power electronics industry based on silicon carbide (SiC) has rapidly expanded, but suppliers are struggling to meet the market demand both for final devices and for the starting raw material, which nowadays consists of SiC wafers with a diameter of 150 mm (6 inches). For this reason, the top industrial players in the field of SiC power electronics are starting the development of next-generation wafers with a diameter of 200 mm (8 inches). This work describes the recent achievements in the implementation of the world's first industrial pilot line to produce power devices based on 200 mm SiC wafers. In particular, the crystal growth of the 200 mm SiC boules, the slicing and polishing of the wafers, the deposition of the epitaxial layer, and the first tests in the pilot lines are presented.

In this paper an overview on Power Packages challenges and technology approaches is given. These challenges mainly originate from Silicon Carbide MOSFETs superior properties allowing high power, high temperature capability, fast switching transients and high electric field operations. All these features can be obtained in a significant reduced chip area. In order to benefit from the disrupting advantages of these wide band gap semiconductor based power devices, a strong focus on packaging and interconnection technologies is needed to withstand these challenging requirements. In addition one of the major and strong boost for Silicon Carbide technology development is given by the car electrification trend: the strict requirements for the Automotive Market are leading to a design and engineering oriented, since the preliminary stage of development, to optimize the reliability of Power Packages.

This paper presents the characterization and evaluation of current transport properties of power SiC Schottky diode. The evaluation of the main Schottky diode properties is based on the proposed advanced model. This model allows assessing the effect of particular current transport mechanisms with high accuracy. The presence and influence of tunneling current in I-V characteristics are evident, mainly for low temperatures. Unlike previously published results, the proposed model provides a reasonable slight decrease of Schottky barrier height with increasing temperature due to the narrowing of the energy bandgap. The results and model are validated by finite element method (FEM) electrophysical simulations. Evaluated parameters of SiC Schottky diode, such as Schottky barrier height of 1.28 eV and Richardson constant of 1.46 × 106 Am−2K−2 are in good agreement with recent research and FEM simulations.

REACTION is an EU Innovation Action Funded Project which aims to develop the first worldwide 200mm Silicon Carbide (SiC) Pilot Line for SiC based Power technology. The project, which mainly addresses the Smart Mobility societal challenge (car electrification), will allow to match the ever-increasing demand of requirements in terms of quality and cost constraint for next decade generation’s power electronics. A major strength of the project is the complete value chain implementation of the Pilot Line, which integrates and optimizes the cooperation and partnership among producers of 8" SiC substrates and equipment developers, as well as SiC process technologists, RTOs and end-users partners, in order to deliver the final applications. Hence, to achieve innovative SiC power devices with improved performances, along with cost and size reduction, are the most relevant requirements addressed in the project that are expected to lead to a new stronger European supply chain for very compact SiC converters, ideal for the addressed Automotive application.

Wide Band Gap (WBG) semiconductors are increasingly addressed towards Electric Vehicle (EV) applications, due to their significant advantages in terms of high-voltage and low-losses performances, suitable for high power applications. Nevertheless, the packaging in WBG devices represents a challenge for designers due to the notable impact that inductive and capacitive parasitic components can bring in high switching frequency regime in terms of noise and power losses. In this paper, a comparison between conventional Silicon (Si) and emerging Silicon-Carbide (SiC) power switching devices is presented. The effects of inductive parasitic effects and switching frequency are investigated in simulation on a typical switching circuit and power losses are compared as well. Experimental results concerning a SiC-based circuit are shown and investigated in a preliminary printed circuit board (PCB).

In this paper, we have studied the thermal behavior of PFC and LLC stages of an OBC, by means of a FEM simulation. A simplified boundary-dependent thermal model has been used to evaluate the maximum temperature reached by the semiconductor dies. The boundary conditions, which were applied in the model, are the heat source (power losses) and the heatsink (cooling system). The obtained results highlight that, if the baseplate temperature is fixed at 60 °C, the maximum rated temperature reached by the power semiconductor devices at full load is 78 °C, well below 100 °C. The simulated temperature profiles can be used for accurate life-time estimation of the power devices in long-term mission profiles framework. We can conclude that, despite the minimum footprint, the result guarantees excellent reliable continuous operation and scalability and it is fully compatible with the car technology, and suitable to be installed on board. Future works will be deal with the generation of more accurate models of the board and of the devices, as well as the passive components inclusion in the simulation, and the transient system’s thermal performances.

The presented analysis has been aimed to evaluate the impact of die solder and sintering solution for automotive power modules in terms of thermal behavior. First, dedicated temperature measurements have been performed to evaluate the module thermal impedance in the two cases. Then, a lumped equivalent networks has been calculated, by means of a dedicated numeric, and finally function structures have been extracted

In this paper, a preliminary PCB board for the electromagnetic interference (EMI) characterization of innovative silicon-carbide (SiC) based switching devices is presented. Packaging technological issues can determine hurdles in the high-frequency switching and high power regime where wide band gap semiconductors are intended today for Electric Vehicle (EV) applications. In particular, the parasitic inductances that emerge in such devices, must be assessed, by using e.g. EMI techniques. In this specific case, the EMI characterization is supposed to be carried out in a semi-anechoic chamber, available at the University of Palermo (UNIPA), to assess the electromagnetic disturbances according to the levels of compliance indicated by the standards. The proposed prototype can work properly at the following levels of voltage, frequency and load power: 28.5 V, 2 MHz and 40 W. Details concerning the layout design and the prototype manufacturing are discussed.

Nickel silicidation reactions were activated on 4H-SiC using laser annealing at wavelength of 308 nm to study interaction and reaction of the involved atomic species. With this intent, the deposited nickel layer thickness was scaled from 100 nm to 10 nm and the laser fluence was spanned from 2.2 to 4.2 J/cm2. A combination of structural characterization by X-ray diffraction, Energy-Dispersive X-ray spectroscopy, Raman Spectroscopy, Transmission Electron Microscopy and morphological investigations through Scanning Electron Microscopy with theoretical predictions as a function of the applied laser fluence, have unveiled that the starting nickel thickness plays a main role, especially above the threshold for nickel melting (2.8 J/cm2). As a general paradigm, sufficient silicon release from the substrate occurs above this threshold that is available for silicidation, with amount increasing with the laser fluence. This addresses stoichiometry and morphology of the silicided contact that indeed depend on the available Nickel atoms (i.e., the Ni layer thickness) and on the thermal profile, as tested at a fixed fluence of 3.8 J/cm2. In addition, a layer-by-layer variable stoichiometry is established in each sample through the contact, with the deepest silicide being relatively more Si-rich. All those findings have impact on the electrical parameters of testing diodes. Based on data cross-linking, NiSi2 contacting layers and C-free interfaces provide a convenience in reducing resistance contributions.

This study investigates the surface topography of the deposited thin films versus the distance between target and substrate (dTS) inside a laser ablation equipment. The profile of the rough surface was obtained by atomic force microscopy data analysis based on power spectral density and the roughness-length scale (RLS) functions. The roughing on the top film is analyzed considering the previous topography of the underneath surface for each consecutive TiO2 and Si deposition onto Si (100) wafer. The buried oxide layer inside of Si/TiO2/c-Si structure, obtained by KrF excimer laser ablation was characterized by complementary techniques as spectral ellipsometry, X-ray reflectometry, and X-ray diffraction.