1. Design of an 8-Channel 40 GS/s 20 mW/Ch Waveform Sampling ASIC in 65 nm CMOS
- Author
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Park, Jinseo, Angelico, Evan, Arzac, Andrew, Braga, Davide, Datta, Ahan, England, Troy, Ertley, Camden, Fahim, Farah, Frisch, Henry J., Heintz, Mary, Oberla, Eric, Pastika, Nathaniel J., Rico-Aniles, Hector D., Rubinov, Paul M., Wang, Xiaoran, Yeung, Yui Man Richmond, and Zimmerman, Tom N.
- Subjects
Physics - Instrumentation and Detectors ,High Energy Physics - Experiment - Abstract
1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in the TSMC 65 nm process targetting 1 ps resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing ps time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC., Comment: 16th Pisa Meeting on Advanced Detectors
- Published
- 2024