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System integration for LED lighting is facing the challenge of providing many additional smart functions in one housing of small form factor. A possible way to integrate more functionality into smaller volume is a system in package (SiP) approach which combines e. g. logic and power chips. Chip-embedding in laminate technology based on copper leadframes is an attractive technology for SiP. In this paper we show how to enable chip-embedding technology to integrate both logic and power functions in one package. As key enablers we identified diffusion soldering die-attach for power dies, laser direct imaging for structuring of low parasitic redistribution layers, warpage and distortion compensation, and complexity reduction in material processing. We present the results of a functional LED light engine built with our flexible 3D-SiP approach based on chip-embedding in laminate. The footprint of the light engine’s power supply subsystem could be reduced by a factor of 3.8 in comparison to using standard packaged components. We verified a process chain for 3D-assembly of surface mount devices on top of the chip-embedding package, and for soldering of this 3D-SiP to the light engine board. The manufacturability of the 3D-SiP we demonstrated in a productive surface mount technology line.

We investigate the reliability of a system-in-package (SiP) technology, which uses laminate chip embedding based on a copper leadframe. For this SiP technology, we apply different Si-based transistor technologies. We test the reliability of three types of chip-embedded packages: a single-chip embedded package (SCP) with an embedded MOSFET test chip for basic understanding, and two SiPs—a multichip embedded package (MCP) with a dc/dc converter for industrial applications and a SiP for lighting applications. In order to better represent specific field stresses for the target applications, we develop and investigate new test methods for laminate-based packages. In this article, we report the design, the implementation, and the results of those new methods and discuss their benefits and validity. We conducted conventional test methods like temperature humidity bias (THB) for comparison. The results of all these tests demonstrate a very good reliability of the chip-embedded packages. We also investigate early damages inside the packages using failure analysis techniques such as cross sectioning. The cooperation of partners along the value chain resulted in a coherent understanding of chip-package-board material aspects and design for reliability.

This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high. The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production.

Laminate chip embedding tailored to very thin dies is an attractive package technology for the integration of logic and power dies. In this paper we report on a new leadframe based laminate chip embedding technology. Best benefit from this technology can only be achieved if experience from silicon front-end, assembly and packaging, as well as from printed circuit board research is combined and consequently applied. We demonstrate the importance of close interaction between Si-frontend and assembly and packaging technology on three examples of applied materials and process research: First, we show in a comparative study that glass fiber filled resin systems result in superior package reliability as compared to filled systems without glass fibers. Second, we present a novel approach to avoid lamination voids by process simulation based on the Monte-Carlo method. Third, we describe the mechanism of laser induced chip metallization damages during contact opening. We also present measures on how to avoid these damages. Our results show that careful selection of laminate materials and chip back-end-of-line materials are the key success factors for stable processes and reliability.

Die Leistungselektronik-Komponenten in heutigen Hybridfahrzeugen sind an unterschiedlichen Orten im Fahrzeug untergebracht - bisher noch jenseits eines rauen und heissen "Umfelds". Um eine integrierte, getriebenahe Loesung zu entwickeln, haben ZF und BMW das Forschungsprojekt "Elektrokomponenten fuer Aktivgetriebe" (EfA) ins Leben gerufen. Auf Basis eines Achtgang-Vollhybridgetriebes entwickeln sie mit Infineon, Kemet und Liebherr sowie der Technischen Universitaet (TU) Chemnitz eine Leistungselektronik-Einheit, die eine Verdoppelung der Leistungsdichte bei gleichzeitiger Erhoehung der Betriebstemperatur ermoeglicht. Die Leistungselektronik soll bauraumneutral am Getriebe untergebracht werden koennen. Voraussetzung hierfuer ist eine Verkleinerung aller Komponenten und ein modifiziertes Kuehlkonzept. Die TU Chemnitz erbringt den Lebensdauernachweis fuer die Neuentwicklung des Leistungsmoduls von Infineon. Kemet stellt den hochkompakten temperaturfesten Zwischenkreiskondensator zur Verfuegung und Liebherr-Elektronik entwickelte eine hochkompakte, fuer den Betrieb mit Verbrennungsmotorkuehlwasser geeignete Steuerelektronik. Von Bedeutung war es, thermisches, mechanisches und EMV-Design bauraumoptimal darzustellen. Mit dem Efa-Projekt ist es gelungen, die Leistungselektronik bei gleichzeitig deutlicher Erhoehung der thermischen Anforderungen auf 14 kW/I zu verdichten.

places in the vehicle – till now far away from harsh and hot surroundings. In order to develop an integrated solution near the transmission, ZF and BMW launched the research project “Electric components for active power transmissions” (EfA). On the basis of an eight-speed full hybrid transmission and together with Infineon, Kemet, Liebherr, and the University of Technology of Chemnitz, they are developing a power electronics unit, which facilitates doubling the power density while increasing the operating temperature. The project EfA will be concluded in June 2011. ThIrd GEnErATIOn hyBrId drIvE: TrAnsMIssIOn-BAsEd InTEGrATIOn OF pOWEr ELECTrOnICs

A solution for the wiring problem in highly complex and embedded systems is the technology of three-dimensional integration. This approach allows a high interconnect density between two or more chips with very short signal or power lines. With the chip stacking concept shown here, a via density of up to 4400 vias per mm 2 is obtained for a chip thickness of 10 μm. However, in this technology it seems also important to implement already fully processed CMOS and memory circuits and thus only frontend and backend processes are considered. This limits the maximum processing temperature to 300 °C to avoid any degeneration in pre-processed circuits. First results show very low leakage currents as well as very low through resistances.

In this investigation we present a novel technology for three-dimensional integration of diamond sensors and actuators. Based on a previously developed technology for the integration of a 3-D CMOS camera stack, in this attempt nano-crystalline diamond layers on silicon are used at the sensor level. The processing steps involve silicon thinning, through-silicon etching and metallization, as well as a soldering process using inter-metallic diffusion. Strong emphasis lies on a low thermal budget process, making the technology suitable for backend processing. The concept is demonstrated, however active CMOS chips are not yet implemented. First electrical measurements of the through-connected UV sensors are presented.

In this work we present a bi-stable diamond micro-bridge with a centre operating contact, which can be used in various fields of application. The actuator is based on the thermal bi-metal actuation principle, switching a double anchored cantilever beam between two bi-stable positions as described previously [P. Schmid, F. J. Hernandez-Guillen and E. Kohn, Diamond and Related Materials, 12 (2003), pp. 418–421]. The actuator device is composed of two parts: (a) the beam actuator (which enables a bi-stable vertical movement of an operating contact) with frame and pillars, and (b) the base plate, which contains the contact base. The bi-metal actuator principle allows the generation of large forces acting onto the base, since the base-plate technology is independent from that of the actuator. Hybrid integration of this system offers applications in various fields. Several examples are proposed and described.

The current technology in micro-and nano-electronics is insufficient to meet future demands for several applications. Most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Our approach implements an epitaxial etch-stop layer for thickness control of the thinning process. Using this etch-stop layer, we can create a precise alignment of back-side vias to the landing pads in the first metal layer of the active CMOS, resulting in small via diameters and high connection densities between individual-layers of the 3D stack. Furthermore, we can use other materials, like GaAs (gallium arsenide), in combination with an epitaxial lift-off process. We use a copper-tin soldering process based on the solid-liquid interdiffusion (solid) process to create the electrical and mechanical connection between the single chip layers. Using this process, we created true multilayer stacks and tested them with respect to the static electrical properties of ohmic contacts and interchip vias. We directly incorporated these results in the design of test circuits that create tests for stuck-at failures of the interchip connections after stack assembly. This article presents a technology overview of how to achieve the goal in a 3D fabrication process. It also shows measurements for characterizing interconnects.

In der vorliegenden Arbeit wird eine Built-In Self-Test Schaltung (BIST) vorgestellt, welche die vertikalen Inter-Chip-Verbindungen in einer neuartigen 3D Schaltungstechnologie auf ihre Funktionalität zur Datenübertragung überprüft. Die 3D Technologie beruht auf der Stapelung mehrerer aktiver Silizium-CMOS-ICs, welche durch das Siliziumsubstrat hindurch vertikal miteinander elektrisch verbunden sind. Bei diesen Vias sind die zu erwartenden Defekte hochohmige Verbindungen und Kurzschlüsse. Die entwickelte Testschaltung ermöglicht es, beliebige Konstellationen von vertikalen Verbindungen auf Fehler zu untersuchen, und das Ergebnis entweder zur Analyse der 3D Technologie auszulesen oder innerhalb des Chipstapels zu verwenden, um defekte Vias zu umgehen. Die Schaltung wurde in einer 0,13μm Technologie entworfen und simuliert. Ein Testchip ist momentan in Produktion.

Surface microfluidic elements are an essential part of lab-on-a-chip systems to perform complex chemical and biochemical synthesis as well as analyical tasks. These systems typically consist of channels, mixers and reaction chambers but also of actuators like pumps, heaters, etc., and sensors, measuring temperature, flow, impedance, pH, etc. To integrate these different functionalities, it is usually necessary to utilize different material systems [Eur. J. Pharm. Sci., 20(2) (2003) 149–171; Adv. Drug Delivery Rev., 55(3) (2003) 349–377]. Due to the unique properties of diamond, e.g. chemical inertness, UV transparency, high thermal conductivity and its semiconducting property, diamond can be universally used as base material for both passive and active elements. In previous work, the realization of temperature sensors, UV sensors and experimental ion sensitive FETs [Diamond Relat. Mater. 12 (2003) 554–559] has already been demonstrated. Various actuation principles like electrostatic [Diamond Relat. Mater. 12 (2003) 418–421], bubble-jet [Diamond Relat. Mater. 10 (2001) 722–730] and bi-metal actuators [Technical Proceedings of the 2003 Nanotechnology Conference, San Francisco, USA, February 23–27, (2003) pp. 380–383] have also been employed. This paper presents a new approach to the fabrication of all-diamond surface channels and chambers to link the different elements together and to provide a covered fluidic pathway. This needs high aspect ratio geometries and was obtained by modifying the common dielectric sacrificial layer technology used for MEMS [J.W. Gardner, Microsensors-Principles and Applications, John Wiley and Sons, Chichester, UK, 1994, p. 52ff], that is replacing the silicon dioxide by electroplated metal. Using an electroplating process, high thicknesses can be obtained. The sacrificial metal layer is then overgrown with diamond. As a first example, an integrated micro-membrane pump with thermal actuation is discussed.

Scaling of microjoints in 3-dimensional chip stacks is proposed by means of kinetic control. Therefore, phase growth in the copper/tin system in presence of various metal barriers at the interface is evaluated. Promising results have been obtained by using layers of Ti, Ta, Ti: W or combilayers thereof in a thickness range of 20 to 50 nm. The lack of wetting ability observed in some cases, could be overcome by thermal pretreatment in order to promote phase nucleation before tin melting.

In this contribution, the use of CVD diamond as a multi-functional material for DC coupled microwave switches is discussed. CVD diamond is a new MEMS material with extraordinary properties, especially for heavy duty applications in extreme environments. An all-diamond cantilever based switch is described using two different actuation principles. First results for a coplanar waveguide configuration are presented.

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