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In this work the relationship between changes in wafer center bow after thinning process and the wafer morphology has been shown. KOH wet etching allowed the observation and counting of dislocation in 4H-SiC substrate. In deep a correspondence between changes in wafer center bow and the dislocation density of the SiC substrate has been observed. By using a counting software, a relationship with the basal plane dislocation and center bow has also been observed.

In this work, the effect of high temperature molten KOH wet etching on GaN/AlGaN epilayer has been investigated for different family of dislocations. The high etching temperature (up to 510°C) allows a good definition of the pits, making easy the observation and the counts. Such high temperature will allow a detailed study on the statistical distribution of the dislocations on whole wafer by optical microscope for screw/mixed dislocation. A comparison on dislocation density between AlGaN/GaN structure grown on Si (111) substrate and 4H-SiC substrate has been performed.

In this work the intrinsic and induced defects related to the mechanical strength of 4H-SiC wafer have been investigated by considering substrates having different dislocation density and subjected to different treatments such as thinning process and high temperature bulk and laser annealing. Three point bending test has been performed on die extracted from the substrates in order to calculate the stress σ the die can withstand at breakage (flexural strength). The variation of intrinsic defect density seems does not act to modify the material flexural strength. Conversely, a considerable correlation between the induced defect density and flexural strength has been found.

In this work the effect of the ion implantation on the dislocations structure of the 4H-SiC epilayer after the KOH etching has been investigated. The study was conducted using both Aluminum (Al) and Phosphorous (P) species for p-type and n-type, respectively. The ion implantations of Al and P were carried out at different energies (30–200 keV) to achieve 300 nm thick acceptor box profiles with a concentration of about 1020 at/cm3. The implanted samples were annealed at high temperatures. With sequential sacrificial and stopping layer both species has been implanted on the same sample. Morphological charaterization of the samples (optical microscope and SEM) shown different structural modification of the dislocations (experically TED) after the KOH etching of the samples.

It is commonly thought that, in the development of SiC power devices with low on-state resistance (Ron), several critical processes in the device fabrication line can strongly impact the final warpage of wafers. High warpage would lead to bad definition of masks, preventing uniform deposition of resist materials and disturbing the normal handling procedures. All these factors would then result in a potential decrease of the electrical yield of the devices, especially for MOSFETs. This study reveals the lack of correlation between critical line processes such as epitaxial growth, oxidations, ion implantations, annealing processes with the final bending of wafers. Conversely, a strong dependence with the resistivity of the substrates is observed. A new parameter defined as RMR (Resistivity Modulation Rate) is taken proposed and, together with the starting value of ingot resistivity, this parameter shows a strong relationship with the final warpage after wafer thinning. A safe region having warpage low enough to allow the workability of the wafers is found.

In this study, the correlation between the Emission Microscopy (Em.Mi.) related to the failure site of the 4H-SiC 650V MOSFET devices after reliability test and epitaxial dislocation defects is presented. Devices failed at the High-Temperature Reverse Bias (HTRB) test were considered. Device layers have been stripped out by chemical wet etching and etched in a high temperature KOH solution to characterize defects emerging at the SiC surface. This approach was used to correlate failure emission spots with underlying structure of the material. KOH etching process on delayered devices was performed at 500°C for 10 minutes and then analysis by optical microscopy and SEM was carried out for defect classification and correlation with failure location.

In the development of SiC MOSFETs, further improvements are ongoing to improve device performances. One of the critical part at the device level is the gate oxide/semiconductor interface, being the gate oxide a standard SiO2 layer. This work is focused on the investigation of the effect of post oxidation annealing process (POA) carried out after the deposition of high-temperature oxide (HTO) layer used for dielectric gate formation by using NO and N2O gasses. The variation of Dit by applying the POA in N2O is considerable with respect to the as-deposited oxide layer as the density is reduced of about two order of magnitude. A further reduction of interface trap density from 2.3×1010 to 8.5×109 traps/cm2 has been observed when NO POA process was applied. Full vertical power MOSFETs were also analyzed in order to measure the channel mobility of the device. Channel mobility has been seen to raise its value from 45 cm2/Vs to a value of about 62 cm2/Vs when NO-based POA process was performed. NO-based POA process results in a much more effective interface at device level.

In this work many steps concerning the epitaxial layer growth on 4H-SiC are studied, evaluated and optimized to obtain high quality 4H-SiC epitaxy. The processes evaluated have been studied on a Hot Wall CVD reactor. The first step related to the substrate surface etching has been tuned by choosing the H2 flow, temperature and process time at which most of defects (mainly stacking faults) are not propagated. Then, the buffer layer step has been optimized by increasing the thickness at which an effective reduction of defect density and an improved electrical performance of power devices have been detected. Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. A crucial step carefully studied has been the drift layer growth. It was optimized by increasing the growth rate (13

Silicon carbide (SiC) is an attractive material for power devices owing to the availability of high-quality epitaxial wafers and superior physical properties, such as its high breakdown electric field strength, high electron mobility, and low anisotropy. Ion implantation is a key process for both n- and p-type selective doping of SiC devices. A subsequent annealing in the temperature range of 1600- 1800°C is required to remove the damage induced by the implantation process and to electrically activate the implanted dopants. The aim of this work is the investigation of the effect of thermal annealing on the damage induced by Phosphorous ion implantation to produce n-type regions.

In this work a deep investigation of the dislocation on 4H-SiC substrate has been shown. The dislocation intersecting the surface were enhanced by KOH etching at 500 deg. C. performed on whole 6 inches substrate. A comparison between basal plane dislocations and threading screw dislocations in the substrate with the defects in the epitaxial layer (mainly stacking faults and carrots) was performed. The comparison between shows a correlation between basal plane dislocations density and stacking faults density maps.

In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.

We present a temperature-dependence electrical characterization of the oxide/semiconductor interface in MOS capacitors with a SiO2layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The post deposition annealing process in N2O allowed to achieve an interface state density Dit 9.0×1011cm-2eV-1below the conduction band edge. At room temperature, an electron barrier height (conduction band offset) of 2.8 eV was measured using the standard Fowler-Nordheim tunneling model. The electron conduction through the SiO2insulating layer was evaluated by studying the experimental temperature dependence of the gate current. In particular, the Fowler-Nordheim electron barrier height showed a negative temperature coefficient (dφB/dT= - 0.98 meV/°C), which is very close to the expected value for an ideal SiO2/4H-SiC system. This result, obtained for deposited SiO2layers, is an improvement compared to the values of the temperature coefficient of the Fowler-Nordheim electron barrier height reported for thermally grown SiO2. In fact, the smaller dependence ofφBon the temperature observed in this work represents a clear advantage of our deposited SiO2for the operation of MOSFET devices at high temperatures.

This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.

This paper reports on the electrical activation and Ohmic contact properties on p-type Al-implanted silicon carbide (4H-SiC). In particular, the contacts were formed on 4H-SiC-implanted layers, subjected to three different post-implantation annealing processes, at 1675 &deg, C, 1175 &deg, C, and 1825 &deg, C. Under these post-implantation annealing conditions, the electrical activation of the Al dopant species increased from 39% to 56%. The Ti/Al/Ni contacts showed an Ohmic behavior after annealing at 950 &deg, C. The specific contact resistance &rho, c could be lowered by a factor of 2.6 with the increase of the post-implantation annealing temperature. The result can be useful for application in device fabrication. Moreover, the dependence of &rho, c on the active acceptor concentration followed the thermionic field emission model, with a barrier height of 0.63 eV.

In this study, we report about an analysis of the crystal quality and stress conditions of aluminum nitride (AlN) buffer layers by changing several process conditions during the growth at a metal-organic chemical vapor deposition (MOCVD) reactor. A two-steps process has been implemented for AlN growth on Si, consisting of a low-temperature AlN (LT-AlN) nucleation step followed by a high-temperature AlN (HT-AlN) growth step. An improvement of the crystal quality has been observed for lower V/III ratio used in the LT-AlN step. Growth temperature of HT-AlN was also examined showing a weak variation of AlN growth rates. Crystal quality and residual stress conditions as a function of the AlN layer thickness were studied. X-ray diffraction (XRD) rocking curves and Raman spectroscopy suggest a better crystal quality when AlN thickness is increased, due to enlargement of islands and reduction of extended defects. After a certain thickness, namely 300 nm, slip lines occurs in epitaxial layers leading to reduction of the residual biaxial stress perpendicular to growth direction. Electrical measurements have been carried out with a critical electric field of 2.1 MV cm−1 achieved.

In this review the effect of the growth process on the formation of defects in the hetero-epitaxial 3C-SiC film and the possible path for defects reduction has been reported. In our analysis of the experimental data we started from the realization of the carbonization layer, the defects at the interface and in the silicon substrate, to the growth of thin and even very thick layers. The discussion has been focalized on the growth on planar blanket Si substrates without the presence of structures or specific buffer layers. Both Chemical Vapour Deposition (CVD) and Sublimation Epitaxy (SE) processes have been reported and studied in detail.

In this work, the conduction mechanisms at the interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures have been studied combining different macroscopic and nanoscale characterizations on bare materials and devices. The AlN/SiN stacks grown on the recessed region of AlGaN/GaN heterostructures have been used as gate dielectric of hybrid metal–insulator–semiconductor high electron mobility transistors (MISHEMTs), showing a normally-off behavior (Vth = +1.2 V), high channel mobility (204 cm2 V–1 s–1), and very good switching behavior (ION/IOFF current ratio of (5–6) × 108 and subthreshold swing of 90 mV/dec). However, the transistors were found to suffer from a positive shift of the threshold voltage during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. To get a complete understanding of the conduction mechanisms and of the charge trapping phenomena in AlN/SiN films, nanoscale current and capacitance measurements by conductive atomic force microscopy (C-AFM)...

Micro Raman characterization has been used to determine the stress status of 3C-SiC epilayer grown on pseudomorphic-Si thin layer on Si1-xGex/Si(001). The strain conditions of the Si1-xGexfilms grown on Si(001) have been determined by the analysis of additional Silicon Raman peaks, which Raman shifts are related to the lattice parameter. Through the analysis of the Raman spectra, the correlation between the Si1-xGexfilm, the crystal quality and the stress relaxation of the 3C-SiC as a function of the Germanium fraction (x), have been evaluated. The increase of Germanium fraction determines the reduction of the voids density located at the 3C-SiC/Si interface and the relaxation of the stress within the epilayer. Moreover, the 3C-SiC crystal quality, monitored by the Full Width at Half Maximum of the TO Raman mode, remains unchanged for any Germanium fraction values.

In this paper we study the influence two different post-growth processes on hetero-epitaxial 3C-SiC on Si substrate for 6 and 8 inches wafers. We studied the influence of wafer cutting process and the substrate partially etching. We find an increase of wafer curvature after each cut processes and every etching processes and a correspondent variation of the Raman shift. These result, confirmed by FEM, can be explained in term of the wafer symmetry breaking and the related relaxation under modified constrains due to the cutting and etching. The FEM analysis of the deformation state reveals a modification of the residual stress tensor which changes from a pure biaxial form to a more complicated one.

3C-SiC shows encouraging physical properties for the development of low cost high power compatible silicon based technology. The fundamental capability of grown 3C-SiC on silicon substrates leads to the possibility of a full integration of Si based process technologies. This is the driving force for the efforts for development a high quality heteroepitaxial film. The fundamental issue is the reduction of defects and stress due to the lattice mismatch between the 3C-SiC epilayer and the Silicon substrate. In this paper we show a way to reduce macroscopic structural features and to enhance the material quality and the surface quality by simply using a process based on a multilayer (ML) buffer structure with n++ and n doping alternation. This process leads to an evident improvement of both surface roughness, morphology and crystal quality.

A study of the carbonization process and of a low temperature buffer layer on the Cubic Silicon Carbide (3C-SiC) epitaxial growth has been reported in this work. From this study it has been evidenced the importance of the C/H2 ratio and of the buffer layer process on the voids formation at the 3C-SiC/Si interface. From our study, the influence of the voids the wafer curvature is highlighted. It has been observed that decreasing the density of these voids, decreases the stress of the 3C-SiC film; consequently, the wafer curvature is reduced.

In this paper we study the surface morphology of 4° degree off, silicon terminated, 4H Silicon Carbide (4H-SiC) in terms of growth parameters and post growth argon thermal annealing. We find that out-of-equilibrium conditions favor the reduction of the surface roughness. Furthermore, we find preliminary indications that the same growth parameters that lead to the reduction of the surface roughness promote also a reduction of (1,3) and (4,4) stacking faults density.

3C-SiC lattice parameters, both in-plane and out-of-plane, have been studied as a function of the temperature (up to 773 K) by performing X-Ray Diffraction (XRD) measurements in coplanar and non-coplanar geometry during the thermal treatments. A tetragonal distortion of the 3C-SiC cell has been observed, with a=b≠c, resulting from a tensile stress status induced by the presence of Si substrate. A linear expansion coefficient of about 4.404 × 10-6 K-1 at 773 K has been obtained for a 15 μm thick 3C-SiC film grown on (100) Si substrate. The discrepancy with the value reported in literature of 5.05 × 10-6 K-1 at 800 K [Slack et al., Journal of Applied Physics 46, 89 (1975)] may be related to the different nature of samples used.

In this work, the growth of high quality 3C-SiC films on Si substrates grown by a hot-wall chemical vapor deposition (CVD) reactor is presented. An increased crystal quality means a reduced crystallographic defect density affecting 3C-SiC films which can be achieved by reducing the growth rate during 3C-SiC heteroepitaxy. In particular, the micro-twin density was observed to decrease with decreasing growth rate allowing for the reduction of theboth the rocking curve and transverse optical Raman mode peak width. Si substrates, both of on- and off-axis orientation, are considered with improvement in crystal quality observed when off-axis substrates are used. Finally, stacking faults and microtwins at the SiC/SiO2 interface are seen to cause non-uniformity in the oxide layer due to the different oxidation rate observed.

Using several types of surface analysis (Optical profilometers (OP), Atomic Force Microscopies (AFM), Scanning Electron Microscopies (SEM) and cross-sectional high-resolution Transmission Electron Microscopies (TEM)) we analyze the surface morphologies of misoriented 4H silicon carbide after pre-growth hydrogen etching and homo-epitaxial growths. We observed the characteristic self-ordering of nano-facets on any analyzed surface. This nano-faceting, which should not be confused with step bunching, can be considered as a close-to-equilibrium instability, for this reason can be hindered.

In this article, using finite element simulations and analytical approaches, we demonstrate that planar rotators[1] can be effectively used to determine both the uniform and gradient residual stresses in thin films with higher accuracy compared to other microstructures.

3C-SiC devices are hampered by the defect density in heteroepitaxial films. Acting on the substrate, it is possible to achieve a better compliance between Si and 3C-SiC. We present here an approach to favorite defect geometrical reduction in both [ ] and [ ] directions by creating Inverted Silicon Pyramids (ISP). A study of 3C-SiC growth on ISP is reported showing benefits in the film quality and a reduction in the linear density of stacking faults. Growth on ISP leads also to a decrease in the 3C-SiC residual stress as well as in the bow of the Si/SiC system.

Growth of 3C-SiC films on an off-axis (111) Si substrate, with a miscut of 4° towards the direction, is here reported. An extensive material characterization has been conducted by means of Scanning Electron Microscopy (SEM), Transmission Electron Microscopy (TEM), X-Ray Diffraction (XRD) and Raman spectroscopy, indicating a very promising film quality with extremely flat surface and interface. Notwithstanding the excellent film quality, the wafer bow is still limiting its full employment in device realization.

A wide characterization of crystalline defects involved in the 3C-SiC heteroepitaxy on Si is here presented. The aim of this work is to show how analysis techniques, such as transmission electron microscopy (TEM) and x-ray diffraction (XRD), can help the researcher in the study of structural defects. The work is focused on stacking faults and microtwins since both of them influence the atomic stacking along the {111} 3C-SiC planes. Their distinction can indeed be troublesome. It will be shown that TEM can be helpful, by choosing a determined zone axis of observation, for defect characterization and distinction. Moreover, the impact of microtwins on the crystal quality of 3C-SiC films is studied by performing XRD pole figures. By means of this technique and simulations, we found that the direction of the SiC crystal is not aligned to the Si direction, but it is shifted of 3.5° along the Si direction, due to second-order twinnings in the 3C-SiC crystal.

SiC is a candidate material for micro- and nano-electromechanical systems (MEMS and NEMS). In order to understand the impact that the growth rate has on the residual stress of CVD-grown 3C-SiC hetero-epitaxial films on Si substrates, growth experiments were performed and the resulting stress was evaluated. Film growth was performed using a two-step growth process with propane and silane as the C and Si precursors in hydrogen carrier gas. The film thickness was held constant at ~2.5 µm independent of the growth rate so as to allow for direct films comparison as a function of the growth rate. Supported by profilometry, Raman and XRD analysis, this study shows that the growth rate is a fundamental parameter for low-defect and low-stress hetero-epitaxial growth process of 3C-SiC on Si substrates. XRD (rocking curve analysis) and Raman spectroscopy show that the crystal quality of the films increases with decreasing growth rate. From curvature measurements, the average residual stress within the layer using the modified Stoney’s equation was calculated. The results show that the films are under compressive stress and the calculated residual stress also increases with growth rate, from -0.78 GPa to -1.11 GPa for 3C-SiC films grown at 2.45 and 4 µm/h, respectively.

The fabrication of SiC MEMS-based sensors requires new processes able to realize microstructures on either bulk material or on the SiC surface. The hetero-epitaxial growth of 3C-SiC on silicon substrates allows one to overcome the traditional limitations of SiC micro-fabrication. In this work a comparison between single crystal and poly crystal 3C-SiC micro-machined structures will be presented. The free-standing structures realized (cantilevers and membrane) are also a suitable method for residual field stress investigation in 3C-SiC films. Measurement of the Raman shift indicates that the mono and poly-crystal 3C-SiC structures release the stress in different ways. Finite element analysis was performed to determine the stress field inside the films and provided a good fit to the experimental data. A comprehensive experimental and theoretical study of 3C-SiC MEMS structures has been performed and is presented.

Raman microscopy has been used to study transport properties in hetero-epitaxial 3C-SiC/Si thin films. By an accurate analysis of the Longitudinal Optic phonon-plasmon coupled (LOPC) modes in n-type doped 3C-SiC films, free carrier density and mobility has been determined. A study of doped 3C-SiC reveals a strong relationship between the calculated free carrier density and both the C/Si ratio used during the epitaxial process and Silicon substrates orientation on which 3C-SiC thin films were grown (maintaining the N2 gas flow rate). The free carrier density obtained is in the range between 5x1016 cm-3 and 4x1018 cm-3. Epitaxial films grown on (111) Si substrates show a higher free carrier density and a lower dependence on C/Si ratios as compared to films grown on (100) Si substrates.

Growth of 3C-SiC on (100) Si has been performed via chemical vapor deposition under two pressure regimes (low and atmospheric pressure) in the early stage of growth. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) have been conducted to study the initial stage of growth while X-ray diffractometry (XRD) and TEM have been used to analyze thicker films and to detect and quantify defects, resulting in a comprehensive and detailed investigation of 3C-SiC structural defects. We have found out that the secondary nucleation of 3C-SiC island growth leads to a higher defect generation rate and, at the same time, to a more effective defect elimination rate. Hillocks found on the surface of thin samples grown under reduced pressure conditions are more pronounced as they seem to be a consequence of twins created in the early stage of growth. Finally, a different initial nucleation density (in the two pressure regimes considered) does not strongly influence stacking fault and microtwin density when growth of thick 3C-SiC films is performed. A very strong influence is indeed observed when 3C-SiC thickness is limited to hundreds of nanometers.

The defects produced by 7.0 MeV C + irradiation in 4H-SiC epitaxial layer were followed by Deep Level Transient Spectroscopy, current-voltage measurements and Transmission Electron Microscopy in a large fluence range (10 9-5?ó10 13 ions/cm 2). At low fluence (10 9 -10 10 ions/cm 2), the formation of three main level defects located at 0.68 eV, 0.98 eV and 1.4 eV below the conduction band edge is detected. The trap concentration increases with ion fluence suggesting that these levels are associated to the point defects generated by ion irradiation. In this fluence range the leakage current of the diodes does not change. At higher fluence an evolution of defects occurs, as the concentration of traps at 0.68 eV and 1.4 eV decreases, while the intensity of the level at 0.98 eV remains constant. In this fluence range complex defects are formed and an increase of a factor five in the leakage current is measured. ¬© (2009) Trans Tech Publications.

The fabrication of SiC MEMS-based sensors requires new processes able to realize microstructures on bulk material or on the SiC surface. The hetero-epitaxial growth of 3C-SiC on silicon substrates allows one to overcome the traditional limitations of SiC micro-fabrication. This approach puts together the standard silicon bulk microfabrication methodologies with the robust mechanical properties of 3C-SiC. Using this approach we were able to fabricate SiC cantilevers for a new class of pressure sensor. In the present research, chemical vapour deposition (CVD) in the low pressure regime of 3C–SiC on silicon substrates was carried out using silane (SiH4), propane (C3 H8) and hydrogen (H2) as the silicon supply, carbon supply and gas carrier, respectively. The resulting bow in the MEMS structures was evaluated optically and the residual stress in the films calculated using the modified stoney equation and determined to be approximately 300 MPa.

The choice of off-axis (111) Si substrates is poorly reported in literature despite of the ability of such an oriented Si substrate in the reduction of stacking faults generation and propagation. The introduction of off-axis surface would be relevant for the suppression of incoherent boundaries. We grew 3C-SiC films on (111) Si substrates with a miscut angle from 3° to 6° along and . The film quality was proved to be high by X-Ray diffraction (XRD) characterization. Transmission electron microscopy was performed to give an evaluation of the stacking fault density while pole figures were conducted to detect microtwins. Good quality single crystal 3C-SiC films were finally grown on 6 inch off-axis (111)Si substrate. The generated stress on both 2 and 6 inch 3C-SiC wafers has been analyzed and discussed.

We have developed a high-quality growth process for 3C-SiC on on-axis (111)Si substrates with the ultimate goal to demonstrate high quality and yield electronic and MEMS devices. A single-side polished 50 mm (111)Si wafer was loaded into a hot-wall SiC CVD reactor for growth. The 3C-SiC process was performed in two stages: carbonization in propane and hydrogen at 1135°C and 400 Torr followed by growth at 1380°C and 100 Torr. X-ray diffraction rocking curve analysis of the 3C-SiC(222) peak indicates a FWHM value of 219 arcsec. This is a very interesting result given that the film thickness was only 2 µm, thus indicating that the grown film is of very high quality compared with published literature values. X-ray polar figure mapping was performed and it was observed that the micro twin content was below the detection limit. Therefore TEM characterization was performed in plan view to allow assessment of the stacking fault density as well as confirmation of the very low micro twin concentration in this film. TEM analysis indicates a low concentration of stacking faults in the range of 104 cm-1.

The aim of this work is to improve the heteroepitaxial growth process of 3C-SiC on Si substrates using Trichlorosilane (SiHCl3) as the silicon growth precursor. With this precursor it has been shown that it is possible to simultaneously increase the growth rate of the process and avoid the nucleation of silicon droplets in the gas phase. Growth experiments were conducted on three (3) Si substrate orientations in order to assess the impact of the Si substrate on the resulting 3C-SiC film. X-ray Diffraction (XRD), Atomic Force Microscopy (AFM) and Transmission Electron Microscopy (TEM) analysis show the important role of the substrate orientation for the growth process. The different orientation of the substrate modifies the morphology of the 3C-SiC crystalline structure, mostly by changing the density of micro-twins and stacking faults inside the film.

In this work a comparison between atmospheric pressure (AP) and low pressure (LP) carbonization as the first step in the growth process of 3C-SiC on Si substrates is presented. Three different Si substrate orientations have been studied and compared. Characterization analysis has been performed by Atomic Force Microscopy (AFM), X-ray Diffraction Spectroscopy (XRD) and Transmission Electron Microscopy (TEM). XRD and AFM analysis show a lower roughness and a better quality for LPCVD carbonized samples. Substrate orientation plays an important role both in the generation as well as in the effect of such defects in the subsequent growth process, leading to a rougher SiC surface for growth on (110) Si while micro-twin effects are limited for growth on (111) Si, resulting in an extremely flat film.

This study refers, through different microscopies, about the carbonization effects on differently oriented Si surfaces. A statistical study on the relationship between some process parameters (such as temperature, process time) and void dimensions and density, for three Si substrate orientations, is reported.

3C-SiC/Si heteroepitaxy is hampered by large mismatches in lattice parameters (19.7%) and thermal expansion coefficient (8%) leading to 3C-SiC films containing high defects density. To reduce the presence of defects, a multi-step growth process in a CVD reactor is used. The aim of the work is to study the effect of carbonization on differently oriented Si surfaces, experiencing a 200°C-wide temperature range in a CVD reactor, to improve the crystalline quality. TEM analysis are carried out to evaluate thickness, crystal orientations and defects of carbonized layers with respect to the time-dependence of the process and to the different orientations of the Si substrate. It will be shown that process-related defects are strictly correlated to the substrate orientation either for size, density, occupied area, shape or thickness. Uniform, flat and crystalline thin SiC films are obtained with a low defect density.

In this work we analyzed the variation of wafer curvature due to the growth of thin Si layers on top of 3C-SiC/Si films. The final Si/3C-SiC/Si hetero-structure, allows not only to have a deeper understanding of the stress within the different layers, but can also be used for MEMS applications, using the Si film as sacrificial layer in order to obtain 3C-SiC free-standing structure, or for electronic application, e.g. using the thin Si layer as high quality MOSFET channel and the SiC layer as the drift region. In details, the influence on wafer curvature by the growth of thin Si layer on top on the 3C-SiC/Si film as been studied by optical profilometer. A theoretical model was also applied in order to fit the measured curvature of the hetero-structure and optimize the system. Finally, in order to study the morphology of the hetero-structure micro-Raman spectroscopy and Transmission Electron Microscopy (TEM) measurements has been performed. © (2014) Trans Tech Publications, Switzerland.

We discuss the possible source of surface instabilities (with specific reference to the step bunching phenomena) during the growth of cubic and hexagonal Silicon Carbide polytypes. For this analysis we use: results from super-lattice Kinetic Monte Carlo simulations, atomic force microscope surface analysis and literature data. We show that only hexagonal polytypes with misorientation cut toward the direction suffer "intrinsically" the step bunching phenomena (i.e. it are present, independently on the growth conditions) whereas cubic polytypes and hexagonal ones with misorientation cut toward the direction do not. © (2009) Trans Tech Publications, Switzerland.

Silicon carbide is a semiconductor material with ceramic-like properties and can be formed in amorphous, polycrystalline, and single crystal forms. SiC single crystals form various polytypes with hexagonal forms, 4H-SiC and 6H-SiC, grown in bulk form for wafer production, and the only cubic form, 3C-SiC, grown via thin film deposition. In this chapter, a review of methods to synthesize all three forms of SiC is presented along with their respective properties which impact their use in biological systems. Several challenges exist that make the growth of high quality, single-crystal silicon carbide films difficult. Fortunately, SiC’s superior material properties, which make it beneficial for use as a material in biological systems, also appear to be present in the “easier-to-deposit” amorphous and polycrystalline forms. Chemical vapor deposition and sputtering has proven to be a powerful deposition technique that is frequently employed when thin films of monocrystalline, polycrystalline, or amorphous-SiC are desired. Several substrates are available upon which thin SiC films are deposited. Commercially produced SiC wafers provide a platform on which SiC films of the same polytype can be grown for electronic junctions, whereas silicon substrates can be patterned or processed with the intent of improving the quality of the SiC thin films or simplifying SiC device fabrication. Silicon substrates, thus, provide an interesting low-cost and large area template for SiC thin films with attractive scientific challenges for the researchers’ community. The large array of options available for SiC synthesis should prove attractive for device design and fabrication, particularly for SiC bioMEMS.

Growth of single crystal 3C-SiC films on large area off-axis (111) Si substrate by chemical vapour deposition technique is here reported. The growth was conducted on off-axis Si substrates due to the ability of the misorientation to reduce anti-phase disorder in the 3C-SiC film. 3C-SiC films show an extremely flat surface and interface, stimulating further interest for electrical and mechanical device applications even if a very strong bow, due to the strain induced by the growth process, is observed. Film quality was proved to be high by several investigation techniques and a study of the crystalline defects is also presented. Optical profilometer measurements were also conducted to evaluate accurately the asymmetric curvature of the whole system.