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Poster session 2, September 22, 2022, 12:30 PM - 1:30 PM It is known that the incidence and epidemiology of candidemia vary according to different geographic regions and/or hosts. Between 1998 and 2019, the incidence in a university hospital in the city of Buenos Aires Argentina, ‘HCJSM’, was 2.19/1000 discharges. The coronavirus disease 2019 (COVID-19) pandemic altered the previously recognized course of severe infections, including candidemia. Objective The aim of this report is to determine the incidence of candidemia in critically ill COVID-19 patients, and the clinical and microbiological aspects of these episodes hospitalized at HCJSM. Methods The source documents of this retrospective study are medical records from patients with Sars-Cov-2 and candidemia who were diagnosed between March 1, 2020 and June 30, 2021. At the onset of the pandemic, the HCJSM began admitting patients with COVID-19, and elective procedures were canceled. Demographic, clinical, and laboratory data were reviewed. All data were analyzed using RStudio, a statistical computing platform (version 4.0.2). Results During the period under review, 61 episodes of candidemia were identified: 23 episodes (39.7%) in COVID-19 patients, and 38 episodes (60,3%) in no COVID-19 patients. Incidence (x 1000 admission) in no COVID-19 patients was 2.5 (38/14 903): in COVID-19 patients 14.4 (23/1595) and in COVID-19–ICU was 42.3 (20/472). The average age of patients is of 65 years (32-84 range years). The time from admission to ICU to the development of candidemia had a median of 18 days (RIC 9-23). A total of 87.5% of the patients had been on mechanical ventilation and 100% of the patients received broad-spectrum antibiotics and had catheters. Episodes were caused by C. parapsilosis (39.7%), C. albicans (35%), C. glabrata (14%), and other species of Candida (11%). A total of 62% of COVID-19 patients who developed episodes of candidemia died during the period under examination. The survival likelihood at 30 days of COVID-19 patients who developed candidemia was higher for C. parapsilosis episodes and lower for C. glabrata episodes. Conclusion The incidence of candidemia showed an increase in COVID-19 hospitalized severe patients. The use of broad-spectrum antibiotics, the presence of catheters, and the use of ventilatory support in COVID-19 patients were the risk factors most associated with the development of candidemia. Although the number of episodes of candidemia is low, without the strength of statistical analysis, it is important to consider that the likelihood of survival of patients with episodes of candidemia varies according to the species recovered.

We use a multi-scale modeling to study the time-dependent dielectric breakdown of an amorphous (a-) HfO[Formula: see text] insulator in a metal–oxide–metal capacitor. We focus on the role played by electron injection in the creation of oxygen vacancies, which eventually form the percolation path responsible for dielectric breakdown. In this scenario, the electron transport through the dielectric occurs by multi-phonon trap assisted tunnelling (MPTAT) between O vacancies. Energy parameters characterizing the creation of oxygen vacancies and the MPTAT process are calculated using density functional theory employing a hybrid density functional. The results demonstrate that the formation of neutral O vacancies facilitated by electron injection into the oxide represents a crucial step in the degradation process dominating the kinetics at common breakdown fields. We further show the importance of the so-called “energetic correlation” effect, where pre-existing O vacancies locally increase the generation rate of additional vacancies accelerating the oxide degradation process. This model gives realistic breakdown times and Weibull slopes and provides a detailed insight into the mechanism of dielectric breakdown and atomistic and electronic structures of percolation paths in a-HfO[Formula: see text]. It offers a new understanding of degradation mechanisms in oxides used in the current MOSFET technology and can be useful for developing future resistive switching and neuromorphic nanodevices.

We investigate 3D charge-trap (CT) nand flash cells using device-physics based multi-scale simulations to explore their potential and optimum operating conditions as electronic synapses of the neuromorphic hardware. A set of figure of merits (FOMs) has been adopted to indicate their goodness of operation under incremental pulse inputs. The results of this study suggest that excellent synaptic FOMs can be attained from 3D CT nands by designing and calibrating the input pulse trains. The impact of variations of device dimensions on charge capture and release phenomena have been investigated and linked to output characteristics in order to obtain intuitive guidelines for attaining desired synaptic functionalities. By co-designing gate dielectric stack and input pulses, the threshold voltage (VT) of the 3D CT cell can be sequentially increased and decreased in a linear and symmetric fashion, providing a large number of distinct VT levels with good retention characteristics. Statistical simulations suggest that device-to-device variations of electrical responses have a negligible impact on the synaptic capabilities of these devices. It has also been shown that the incorporation of deeper traps through material engineering improves synaptic reliability of the 3D CT cells under prolonged operations.

Dielectric breakdown in 2D insulating films for future logic device technology is not well understood yet, in contrast to the extensive insight we have in the breakdown of bulk dielectric films, such as HfO2 and SiO2. In this letter, we investigate the stochastic nature of breakdown (BD) in hexagonal boron nitride (h-BN) films using ramp voltage stress and examine the BD trends as a function of stress polarity, area, and temperature. We present evidence that points to a non-Weibull distribution for h-BN BD and use the multi-scale physics-based simulations to extract the energetics of the defects that are precursors to BD, which happens to be boron vacancies.

We present a defect spectroscopy technique to profile the energy and spatial distribution of defects within a material stack from leakage current ( ${J}$ – ${V}$ ), capacitance ( ${C}$ – ${V}$ ), and conductance ( ${G}$ – ${V}$ ) measurements. The technique relies on the concept of sensitivity maps (SMs) that identify the bandgap regions, where defects affect those electrical characteristics. The information provided by SMs are used to reproduce ${J}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data measured at different temperatures and frequencies by means of physics-based simulations relying on an accurate description of carrier-defect interactions. The proposed defect spectroscopy technique is applied to ZrO2-based metal–insulator–metal structures of different compositions for dynamic random-access memory capacitor applications. The origin of the observed voltage, temperature, and frequency dependencies of the ${I}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ data is understood, and the atomic structure of the relevant stack defects is identified.

III-V RF devices operating at cryogenic temperature are highly desirable for application areas such as space communication or quantum computing. In the case of quantum computation, integration of the readout and control electronics close to the quantum bit (Qubit) stage is needed to allow scaling of the number of Qubits needed for practical applications. Many characteristics of high frequency operation at cryogenic temperature in novel III-V devices are not fully understood. In this study, we will focus on the behaviour of defects at or near the interface between the high dielectric constant (high-k) oxide and InGaAs semiconductor at cryogenic temperature and how it may affect the full device operation at low temperature. The thermal budget constraints associated with the processing III-V semiconductor devices prohibit the use of high temperature thermal treatments to reduce oxide defect densities in the high-k. This leads to defective oxides presenting higher instability, variability, and degradation issues than in the Si/SiO2 system. The methods developed to investigate defects in the Si/SiO2 metal oxide semiconductor (MOS) system generally attribute the divergence in capacitance voltage (CV) and conductance voltage (GV) from the ideal CV and GV characteristics mostly to interface state defects (ITs) [1], which is not the case of the III-V MOS system. As a consequence, attempts to fit the multi-frequency CV and GV response of III-V MOS structures in the weak inversion regime, using interface states alone, cannot recreate the experimental data. In this study, we present an advanced MOS defects characterisation method capable of discerning between the contributions of oxide defects (sometimes labelled ‘border traps’) and ITs. The method relies on the fully physics based simulation of MOS systems, including inelastic tunnelling from the semiconductor to localized defects in the oxide [2] to reproduce the experimental multi-frequency CV and GV characteristics. The simulations include physical models accurately describing the carrier capture/emission processes by oxide traps, and which incorporate tunneling into the dielectric in conjunction with lattice relaxation at the interface/border trap sites [3, 4]. The results will show that the simulations are able to reproduce the room temperature experimental data (both CV and GV) of InGaAs/Al2O3 MOS structures in all bias regions. This new method enables the precise extraction of the density, energy and spatial distribution away from the interface of electrically active oxide defects from different experimental results. Results will also be presented showing how the multi-frequency CV and GV response of n-InGaAs/Al2O3 and p-InGaAs/Al2O3 MOS structures change with reducing temperature. Measurements at 223K show a marked reduction in the CV and GV dispersion with frequency in the accumulation and depletion regions, consistent with a phonon assisted tunnelling interaction of electrons and holes with defects in the Al2O3. Reduction in the measurement temperature to 10K still demonstrates a residual dispersion of the capacitance and conductance with frequency, which is more marked in the case of the p-InGaAs/Al2O3 MOS structure. The models and trap distributions extracted from room temperature will be applied to the reduced temperature measurements (233 K and 10 K) to investigate the validity of the models and to gain further understanding of defect behaviour and associated device implications at cryogenic temperatures. [1] E. H. Nicollian and J. R. Brews, “MOS Physics and Technology,” John Wiley & Sons, New York, 1982. [2] A. Palma, et al. Phys. Rev. B Condens. Matter Mater. Phys., 56 (15), pp. 9565-9574 (1997). [3] E. Caruso, et al. IEEE Trans. Electron Devices, 67 (10), pp. 4372-4378 (2020) [4] G. Sereni, et al. “IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 705–712, (2015).

Discovery of ferroelectricity (FE) in binary oxides enables the advent of FE memories and a plethora of novel CMOS compatible building blocks spanning from the logic domain to high-density storage and neuromorphic computing. In this paper we develop the first comprehensive model of vertical Ferroelectric Field Effect Transistor, V-FeFET, to identify sources of variability, understand retention problems, and point a path to improving reliability and enabling high-density storage FE memories with extended endurance.

Device-to-device variability of CoFeB/MgO based STT-MRAMs is studied based on experiments and simulations taking into account the influence of interface quality, temperature variation and device dimensionality. Metal-induced gap states resulting from electron transfer at the ferromagnet-tunnel barrier interface significantly influence the effective energy barrier height of these devices irrespective of their diameters. Switching voltage and parallel - antiparallel resistance values vary by as much as 43% and 30% respectively for about 13% variation of the energy barrier, whereas the tunneling magnetoresistance remains typically unaffected. WRITE cycles of highly scaled STT-MRAMs are therefore more susceptible to device-to-device variations resulting from microscopic variations in the interface quality, rather than the READ cycles. Such variations are observed to be independent of temperature, as well as spatial distribution of the defects.

Atomic defects in high-k materials affect the performance, reliability, variability, and scaling potential of electronic devices. Their characterization is thus of paramount importance, and methods exploiting electrical measurements are highly demanded. In this work we present a novel method for extracting the defect properties from I-V curve hysteresis measured at low electric field in thick metal-insulator-metal (MIM) stacks. The I-V curve hysteresis allows detecting the defects located near the electrode-insulator interfaces and aligned with the stack Fermi level, and extracting their properties. The defects are profiled cross-correlating the information provided by the low-field current hysteresis and the high-field steady-state current. This technique can be applied to MIM stacks fabricated in Back-End-of-Line for capacitors, embedded memories and thin film transistors.

The ferroelectric HfO 2 based field effect transistor (FeFET) has been under research for many years and shows unique properties for applications in the field of emerging memories and in-memory computing. This work for the first time demonstrates how a target programming algorithm can improve the FeFET device characteristics with respect to endurance performance and variability for small device geometries. With this technique the threshold voltage V t of the memory cell can be targeted to any desired value, which is essential for multilevel cells and analog in-memory computing as used in AI accelerators. The switching, trapping and detrapping characteristics of the cell and their influence on the target programming algorithm are presented. The trapping and leakage characteristics are modelled using the GinestraTM simulation software to extract the trap distribution in ferroelectric HfO 2 . Finally, a model for the underlying mechanism of the endurance degradation is proposed.

The biography of Irnerius (ca. 1055–ca. 1125) and his scientific production remain—chiefly in recent years—one of the most debated and controversial issues among historians. In this chapter, I expound my personal views in the hope of shedding some light on the whole problem. The very first teacher of what, in the following decades, became the University of Bologna, Irnerius boosted the renewed study of the Roman-Justinian law (almost neglected for five centuries) that still today constitutes the basic foundation of the legal Western civilization. In his glosses to the Corpus Iuris Civilis (probably the sole reliable evidences of Irnerius’s activity in the legal field) he revealed himself not only as a refined technician, a subtle logician, and an acute lawyer, but also as a man endowed with a noteworthy religious and ethical sensitiveness leading, in time, to firm and permanent achievements (e.g., in terms of individual freedom, human dignity, and social equity) commonly shared by modern world.

Presence of defects in high-k dielectric materials will affect device’s electrical properties, thus, defect/material characterization is of great importance. We present a simulation-based methodology relying on an accurate description of charge trapping and transport that is useful to extract relevant information on material and defect characteristics. This methodology was applied to cerium oxide and lanthanum oxide high-k dielectric materials and as a result, material properties alongside defect characteristics were extracted. Consequently, main charge conduction mechanism was identified to be trap-assisted tunneling (TAT).

A multiscale simulation platform predicts the effect of atomic level defects in thin films on the electrical characteristics of nanoscale devices and identifies ways to engineer these defects to achieve optimum performance and reliability in logic and memory circuits.

We use experiments and device simulations to investigate pulsed SET operation of HfO2-based RRAM devices for their possible use as electronic synapses. The application of a train of identical pulses only allows for an abrupt change of the device current, which is not suitable for synaptic devices. By using simulations, we link the microscopic properties and changes of the conductive filament during the pulsed operation to the measured conductance and its dependence on pulse voltage, width, and number. The results allow us to derive guidelines that we use to design optimized SET pulses (or pulse trains) allowing extending the conventional binary operation of HfO2-based RRAMs to the multi-level cell operation required by electronic synapses.

The breakdown (BD) sequence in high-K/interfacial layer (HK/IL) stacks for time-dependent dielectric breakdown (TDDB) has remained controversial for sub-45 nm CMOS nodes, as many attempts to decode it were not based on proper experimental methods. Know-how of this sequence is critical to the future design for reliability of FinFETs and nanosheet transistors. We present here the use of radiation fluence as a tool to precisely tune the defect density in the dielectric layer, which jointly with the statistical study of the soft, progressive and hard BD, allow us to infer the BD sequence using a single HfO2–SiO x bilayered MOS structure.

RRAM devices have been subjected to intense research efforts and are proposed for nonvolatile memory and neuromorphic applications. In this paper we describe a multiscale modeling platform connecting the microscopic properties of the resistive switching material to the electrical characteristics and operation of RRAM devices. The platform allows self-consistently modeling the charge and ion transport and the material structural modifications occurring during RRAM operations and reliability, i.e., conductive filament creation and partial disruption. It allows describing the electrical behavior (current, forming, switching, cycling, reliability tests) of RRAM devices in static and transient conditions and their dependence on external conditions (e.g., temperature). Thanks to the kinetic Monte Carlo approach, the inherent variability of physical processes is properly accounted for. Simulation results can be used both to investigate material properties (including atomic defect distributions) and to optimize stack and bias pulses for optimum device performances and reliability.

Editor’s note: Retention time is one of the key parameters of emerging memories, which define the time duration the data can be retained when the power supply is removed. In this work, the authors investigate the forming voltage and the data retention of aluminum (Al)-doped HfO2-based RRAM devices and suggest a way to improve the device’s data retention time. ——Yiran Chen, Duke University

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material&rsquo, s microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device&rsquo, s performance and variability to be evaluated, the analog resistance switching to be optimized, and the device&rsquo, s reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.