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This work presents a 300-GHz low-noise amplifier (LNA) in a SiGe:C 130-nm BiCMOS technology, featuring $f_{t}$/$f_{max}$ of 470/700 GHz. The designed amplifier uses three cascaded stages in a pseudo-differential cascode topology with input and output baluns facilitating single-ended measurements. The first stage is matched trading off noise and gain performance, while a T-type output matching network is used for broadband matching. The interstage matching is performed using center tap transformers. On-wafer measurements show that the designed LNA has a peak small-signal gain of 10.8 dB at 325 GHz, along with a 3-dB bandwidth of 68 GHz and an input 1-dB compression point of -15.6 dBm at 287.5 GHz. The simulated noise figure is better than 12.7 dB over the required band. The circuit occupies 0.26-mm² silicon area and consumes 119 mW from a 3.3-V supply.

In this article, a monolithically integrated single-polarization optical receiver with automatic gain control is presented that shows state-of-the-art performance in terms of bandwidth (BW) and noise. A low-noise technique is applied in a monolithically integrated optical receiver featuring automatic gain and dc-offset cancellation control loops. The electronic and photonic components are fabricated on the same silicon substrate using IHP's 0.25-μm SiGe BiCMOS EPIC technology. The optical receiver features a high tunable transimpedance gain of 66 dBΩ at a large optoelectrical BW of 34 GHz and an input-referred noise current of 2.08 μA $_{rms}$ while consuming only 205 mW of power.

In this paper a transimpedance amplifier is presented, which features a bandwidth of 97 GHz, 66 dBΩ maximum transimpedance gain, and 6.3 pA/√Hz integrated noise current density, operating at up to 120 Gb/s and consuming only 145mW. Reaching a higher bandwidth at a noise performance comparable to the state-of-the-art, is the novelty of this work. It was achieved by combining a low-bandwidth input stage, reducing the total noise, and a multi-stage post equalization. The gain peaking technique through cascading emitter follower stages is employed in a broadband transimpedance amplifier as a post equalizer. To the best of the author’s knowledge, the presented design shows the best performance in terms of overall gain, bandwidth, and noise for the lowest power consumption compared to state-of-the-art designs.

This letter presents a dual-polarization beamformer chip for fifth-generation (5G) applications. The chip leverages a vector-sum phase shifter (VSPS) approach and single-ended design, allowing a reduced control circuitry complexity. The use of the VSPS translates in both phase shift and gain control, as shown in the system analysis. This beamformer is suitable for four dual-polarized antennas, achieving high gain control for each element. The performance can be summarized as a 1-dB compression point of 11dBm, while having an rms phase and amplitude error lower than 0.5° and 0.4 dB, respectively, at the maximum constant magnitude gain circle. Moreover, it is shown that the design can afford tapering despite relying only on the VSPS for gain control.

In this letter, a comparison between two ultra-wideband traveling wave amplifiers (TWAs) designed in two different SiGe:C technologies consuming only 500 mW is presented. The first design utilizes the IHP’s 130-nm SiGe:C BiCMOS SG13G2 technology, featuring $f_{T}/f_{{MAX}}\,\,=300$ /500 GHz, while the second design uses the IHP’s 130-nm SiGe:C BiCMOS SG13G3 technology, featuring $f_{T}/f_{ {MAX}}\,\,=470$ /700 GHz. For a fair comparison, the same architecture has been used for the design of both amplifiers. On-wafer measurements of the SG13G2 amplifier show 15.3 dB gain and 87.4 GHz bandwidth, while the design in SG13G3 technology reaches 16.9 dB gain and more than 110 GHz bandwidth. There is a 1% difference in the output power efficiency where it is 4.1% and 5.1% on SG13G2 and SG13G3 technologies, respectively. In both cases, time-domain measurements show a reliable 120 Gbps non-return-to-zero (NRZ) operation. The presented SG13G3-based TWA shows state-of-the-art performance among similar SiGe BiCMOS amplifiers.

This letter presents a fully integrated three-stage single-ended $D$ -band power amplifier (PA) designed in 0.13- $\mu \text{m}$ silicon–germanium (SiGe) BiCMOS technology. Several bandwidth extension techniques and matching networks are mutually exploited to maximize Bandwidth (BW) performance while assuring unconditional stability. Its measured 3-dB bandwidth covers the entire $D$ -band (110–170 GHz). The PA has a small-signal peak gain of 21 dB at 151 GHz. Its saturated output power ( $P_{\mathrm{ sat}}$ ) in the $D$ -band varies from 11.8 to 13.9 dBm and its output referred 1-dB compression point (OP1 dB) from 9.2 to 12.5 dBm within the $D$ -band. The presented amplifier occupies $0.65\times 0.47$ mm2 (including pads) and draws a current of 115 mA from a 3.3-V supply. To the best of our knowledge, these performances represent the state of the art in silicon technology with a minimum ( $P_{\mathrm{ sat}}$ ) of 11.8 dBm and (OP1 dB) of 9.2 dBm covering the entire $D$ -band.

This letter describes a 96-Gb/s PAM-4 receiver, suitable for silicon photonics application, designed and fabricated in a 130-nm SiGe BiCMOS technology. The low-power receiver includes a TIA and a VGA, two slices of time-interleaved track and hold amplifier and two-bit folding ADC circuits, and multiplexers to deliver full-rate decoded NRZ output signals. The track and hold amplifier is based on a switched emitter–follower topology optimized for low-power operation to sample at 24 GSample/s. Half-rate PAM-4 to NRZ converters are implemented as a bandwidth-enhanced two-bit folding ADC in order to consume less power compared to flash competitors. The receiver chip consumes 545 mW, leading to an energy efficiency of 5.67 mW/Gb/s, which is one of the best among the state-of-the-art works at this data-rate.

This letter presents a D-band (110 to 170 GHz) transmit–receive module in 0.13- $\mu \text{m}$ silicon–germanium (SiGe) BiCMOS for phased-array applications. The module includes single-pole double throw (SPDT) switches, a low noise amplifier (LNA), a power amplifier (PA), and two variable gain amplifiers (VGAs). A broadband quarter-wave SPDT is designed with power handling capacity of 17 dBm and a state-of-the-art insertion loss of 2 dB at 140 GHz. The three-stage cascode LNA and PA and the two-stage phase-compensated VGA cover the entire D-band. In the receive mode, the module has a measured peak gain of 28.3 dB with a 3-dB bandwidth (BW) of 110–170 GHz, along with a minimum noise figure (NF) of 9 dB (at 120 GHz) and an IP1dB of −21 dBm. In the transmit mode, the peak gain is 22.4 dB within a 3-dB BW of 113–170 GHz, while the OP1dB is 7 dBm and the $\text{P}_{\mathrm{ sat}}~9.5$ dBm at 140 GHz.

This letter presents a $V$ -band switchless bidirectional power amplifier-low noise amplifier (PALNA) in a SiGe:C 130-nm BiCMOS technology, featuring $\text{f}_{t}/\text{f}_{\text {max}}$ of 250/340 GHz. This bidirectional PALNA architecture avoids the use of lossy transmit–receive switches by introducing a proper matching network that insures a good isolation when the amplifier is OFF and satisfies the input–output matching requirements when the amplifier is on. On-wafer measurements show that the designed PALNA has a peak small-signal gain of 16.5 and 17 dB in the Tx mode and Rx mode, respectively, with a reverse isolation better than 40 dB while maintaining wideband performance over the desired band from 57 to 66 GHz. In the Rx mode, the simulated noise figure (NF) is 6.5 dB over the required band. Furthermore, a 1-dB compression point (OP1dB) of 11 dBm in the Tx mode and an input 1-dB compression point (IP1dB) of −20 dBm in the Rx mode have been achieved. The switchless PALNA occupies only 0.18 mm2 and consumes 130 and 36 mW in the Tx and Rx modes, respectively.

In this paper, the gap waveguide technology is examined for packaging liquid crystal (LC) in tunable microwave devices. For this purpose, a line based passive phase shifter is designed and implemented in a ridge gap waveguide (RGW) topology and filled with LC serving as functional material. The inherent direct current (DC) decoupling property of gap waveguides is used to utilize the waveguide surroundings as biasing electrodes for tuning the LC. The bed of nails structure of the RGW exhibits an E-field suppression of 76 dB in simulation, forming a completely shielded device. The phase shifter shows a maximum figure of merit (FoM) of 70 °/dB from 20 GHz to 30 GHz with a differential phase shift of 387° at 25 GHz. The insertion loss ranges from 3.5 dB to 5.5 dB depending on the applied biasing voltage of 0 V to 60 V.

This article presents a fully integrated modular wideband frequency interleaving (FI) transmitter and receiver for high data rate communication applications. At the transmitter side, three independent in-phase and quadrature-phase (IQ) baseband channels are upconverted to different intermediate frequencies (IFs) and then interleaved. At the receiver side, the interleaved signals are downconverted and separated back to each independent channel. Single-ended inputs and outputs are utilized to reduce the pin count, for a more practical realization and higher potential toward future system scaling. Special design techniques are followed to minimize crosstalk and intermodulation products between the channels. All circuits are manufactured and measured in a 130-nm SiGe:C BiCMOS technology with $f_{\textbf {T}}/f_{\textbf {max}}$ =300/500 GHz. The FI transmitter achieves a channel bandwidth of 2.5 GHz with less than 3-dB difference across different channels until 15-GHz IF. It consumes 560 mW from 2.5 and 3.3 V supplies and occupies a silicon area of 1.9 mm2. The FI receiver achieves a baseband channel bandwidth of 2.5 GHz with a 1-dB difference between the channels until the same IF. It consumes 860 mW from 2.5 and 3.3 V supplies and has a chip area of 1.55 mm2. The circuits are deployed in a communication experiment; first, in a back-to-back test with a direct cable connection, demonstrating a data rate of 15.6 Gb/s across the three IQ channels with a 16-QAM modulation scheme and a worst case transmitter-to-receiver error vector magnitude (EVM) of −18.6 dB. Then, a wireless experiment is performed with a 240-GHz front end with on-chip antenna, demonstrating a data rate of 7.8 Gb/s with QPSK modulation and a worst case EVM of −8.3 dB, across a wireless link of 15 cm. To the best of our knowledge, this is the first article that demonstrates a wireless transmission at sub-terahertz (sub-THz) carrier frequencies utilizing FI architectures.

In this work, we present a dual window silicon photonic coherent receiver for O- and C-band, fabricated in a 0.25 µm BiCMOS technology. Performance is evaluated for up to 50 GBd, while utilizing a local oscillator power of up to 6.9 dBm.

This work presents a broadband and high power D-band multiplier by 4 chain designed in a 130 nm silicon-germanium (SiGe) BiCMOS technology. A single-ended 35 GHz input signal is made differential by a Marchand balun and multiplied by 4 by means of a Gilbert cell based quadrupler. The undesired harmonics are filtered out by a double section harmonic filter and, after a D-Band Marchand balun employed for differential to single conversion, amplified using a broadband 3-stage cascode amplifier. The presented circuit achieves a 3-dB bandwidth of 60 GHz, covering the entire D-band (110 GHz to 170 GHz) with a peak saturated output power of 8 dBm. A rejection of more than 40 dB has been measured for 3rd, 5th, 6th and 7th harmonics at 140 GHz. The designed circuit consumes 280 mW from a 3.3 V supply, resulting in a drain efficiency of 1.75%. The proposed solution shows a 43 % relative bandwidth, which is, to the best of the authors' knowledge, the largest among the up to now published silicon based D-band frequency multiplier by 4 chains.

This article presents a fully differential power-tuning heterodyne on-chip sensing readout system at 240 GHz. The chip enables the measurement of not only the transmission parameter but also the reflection parameter to sense the permittivity of different materials by using four heterodyne mixer-based receiving channels connected to a dielectric sensing element. To facilitate the operation and characterization, three frequency multiplier chains are included to generate the required two identical radio frequency (RF) and one local oscillator (LO) subterahertz signals. RF frequency multiplier chain is configured to enable a tunable power level of the RF signal by using a variable attenuator. A chip prototype using 130-nm silicon-germanium (SiGe) BiCMOS is implemented with a size of 11 mm 2 and dc power consumption of 2.7 W. The measured 10-dB bandwidth of 20.8% is achieved in a frequency range from 207 to 257 GHz with 14-dB measured power-tuning range. The transmission and reflection parameters' measurements for copper and gummi show a differentiated value in terms of magnitude and phase, which demonstrates the sensing function of the proposed readout system.

In this letter, a wideband power amplifier (PA) and a frequency source (FS) at 240 GHz are presented in 130-nm BiCMOS technology with $f_{ {T}}/{f}_{\text{max}}=$ 300/500 GHz. Two circuits are manufactured and measured. Circuit 1 is a three stage PA with a 4-way zero-degree power combiner (ZDC) and two cascaded 1-to-2 active power splitters. It achieves a gain of 15.5 dB across a linear 3-dB bandwidth of 55 GHz, saturated output power ( $P_{\text {sat}}$ ) of 13.5 dBm, output 1-dB compression point (OP1dB) of 10.5 dBm and a power consumption of 740 mW, resulting in a drain efficiency ( $\eta _{\text {d}}$ ) of 3% and a power added efficiency (PAE) at OP1dB of 1.47%. The presented PA achieves 7-times better PAE with 2-times better $P_{\text{sat}}$ across a bandwidth that is 1.8-times better than the state-of-the-art. Circuit 2 is an FS consisting of a multiplier-by-8 chain driving the PA (circuit 1). The FS achieves a 3-dB bandwidth of 50 GHz with a total power consumption of 990 mW resulting in $\eta _{\text {d}}$ of 2.3%, this is 2-times better $\eta _{\text {d}}$ and 4-times better $P_{\text{sat}}$ compared to literature.

This paper presents a 4-channel bidirectional V-band beamformer adopting a switchless PALNA in a SiGe:C 130 nm BiCMOS technology, featuring ft/f max of 250/340 GHz. Using such technique saves the silicon area occupied by the RF switches avoiding their lossy effect on PAs outputs and LNAs inputs. The designed beamformer contains PAs, LNAs, vector modulators with active balun, passive power dividers/combiners and an integrated SPI interface. On-wafer measurements show that the fabricated beamformer covers the band from 57 GHz to 66 GHz with an average small signal gain of 18 dB and 9 dB all over the channels in both Tx and Rx modes respectively. Furthermore, the beamformer achieves an OP1dB of 10.5 dBm in Tx mode and an IP1dB of −27 dBm in Rx mode. The circuit occupies 11 mm2 and consumes 230 mW and 100 mW per channel in Tx and Rx modes respectively.

In this paper we present a broadband low-noise monolithic-integrated silicon photonic receiver with automatic gain control that shows state-of-the-art performance. The electronic and photonic components are fabricated monolithically on one chip using IHP’s 0.25μm SiGe BiCMOS EPIC technology. The optical receiver features a high tunable transimpedance gain of 66 dBW at a large opto-electrical BW of 34 GHz and an input-referred noise current of 2.81 μA rms while consuming 205 mW of power. Comparing key performance metrics and the functional complexity of similar devices found in the literature, the optical receiver presented in this work achieves an overall superior performance.