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The Minimum Ionizing Particle Timing Detector (MTD) will be introduced in the Compact Muon Solenoid (CMS) experiment to measure the production time of Minimum Ionizing Particles (MIPs). Power Conversion Cards (PCCs) regulates and supplies low voltage to front end electronics of the MTD barrel, the Barrel Timing Layer (BTL). The PCCs host three radiation and magnetic field tolerant DC-DC converters. The physical height of the PCC is limited to 7 mm, having necessitated development of custom inductors and shields. Additionally, the CMS Electromagnetic Calorimeter will be upgraded. On-detector Low Voltage Regulator (LVR) cards host four DC-DC converters and one linear regulator. In these proceedings we will present both cards’ designs evolution, stack-up and layout optimization, noise filtering choices and a performance evaluation., Journal of Instrumentation, 18 (2), ISSN:1748-0221

A series of monolithic active pixel sensor prototypes (APTS chips) were manufactured in the TPSCo 65 nm CMOS imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4 × 4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel pitches (10 µm–25 µm), geometries and reverse biasing schemes were included. Prototypes are fully functional with detailed sensor characterization ongoing. The design will be presented with some experimental results also correlating to some transistor measurements.

The HKROC ASIC was originally designed to readout the photomultiplier tubes (PMTs) for the Hyper-Kamiokande (HK) experiment. HKROC is a very innovative ASIC capable of readout a large number of channels satisfying stringent requirements in terms of noise, speed and dynamic range. Each HKROC channel features a low-noise preamplifier and shapers, a 10-bit successive approximation Analog-to-Digital Converter (SAR-ADC) (designed by AGH Krakow) for the charge measurement (up to 2500 pC) and a Time-to-Digital Converter (TDC) (designed by CEA IRFU group) for the Time-of-Arrival (ToA) measurement with 25 ps binning. HKROC is auto-triggered and includes all necessary ancillary services as bandgap circuit, PLL (Phase-locked loop) and threshold DACs (Digital to Analog Converters). This paper will describe the ASIC architecture and the experimental results of the first HKROC prototype received in January 2022.

The photon detection system of the first far detector (FD1-HD) of the DUNE experiment will detect scintillation photons produced by particle interactions in a kiloton-scale liquid Argon time projection chamber. The photon detectors of choice are silicon photomultipliers (SiPM), 6×6 mm2 each, arranged in groups of 48, which present a significantly low impedance to the front-end electronics. This paper details the design of a cryogenic amplifier with exceptionally low white voltage noise of 0.37 nV√(Hz), based on a silicon-germanium input transistor and a BiCMOS fully differential operational amplifier. It yields excellent single photoelectron resolution even at low overvoltage values. The signal rise time is below 100 ns, and the dynamic range is about 2000 photoelectrons at the typical operating overvoltage. It draws 0.7 mA from a single 3.3 V supply, for a power consumption of 2.4 mW per channel. Simplified models were developed to predict the single photolectron signal shape and the signal to noise ratio, with a good match to measured performance.

This work presents the design and characterization results of a radiation hard bandgap reference circuit fabricated in a 110 nm CMOS technology for the Main Demonstrator chip of the ARCADIA project. The design, based on a current-mode approach in order to be able to output a smaller than 1.2 V reference voltage, employs diode-connected MOSFETs instead of BJTs to enhance the radiation hardness and a second amplifier to improve the current mirror of the output branch and therefore the line regulation of the circuit. This paper describes the features of the circuit and its measured results.

A Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitter’s output is powered with 1.2 V to provide compatibility with previous designs, while the core logic can be powered with 0.8 V to reduce power consumption. This work summarizes the design approach at the schematic and layout level. Practical aspects of the novel technology for the design of ASICs in High Energy Physics will be discussed along with characterization results. Other IP blocks are being designed (ADC, DAC, PLL) and they will be presented.

Serial powering features the upcoming phase II HL-LHC upgrade in the ATLAS and CMS experiment. The conventional voltage based powering approach with parallel placed modules results in low powering efficiency. In addition restricted space requirements, radiation tolerance and high magnetic fields make the design of a suitable DC/DC-converter challenging. To ensure that future DC/DC converters can tolerate high radiation doses at reduced space requirements, a high-frequency switching stage with up to 4 stacked core devices with a related biasing circuit for the implementation in inductive DC/DC-converters was considered and successfully verified in a first prototype.

A radiation-tolerant resonant switched-capacitor DC-DC converter (rPOL2V5) has been developed to supply the front-end analog and digital circuits for the detectors used in the LHC High Luminosity upgrades. It has been of particular interest to the CMS High-Granularity Calorimeter (HGCAL) community due to its lower volume compared to existing radiation-hard buck converters. rPOL2V5 is based on an ASIC developed using 130 nm CMOS technology. It is powered by a 2.5 V input and it can supply a maximum current from 2 A to 5 A, depending on the output voltage value, which can range from 1 V to 1.5 V. This work presents the strategies adopted at the ASIC and PCB level to bring the converter to maturity, and its electrical and radiation characterisation results.

The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the RD53 Collaboration, and in particular its analogue front-end, which receives the signal from the sensor and digitizes it. Three different analogue front-ends (Synchronous, Linear, and Differential) were designed and implemented in the RD53A demonstrator chip. A dedicated evaluation program was carried out to select the most suitable design to build a radiation tolerant pixel detector able to sustain high particle rates with high efficiency and a small fraction of spurious pixel hits. The test results showed that all three analogue front-ends presented strong points, but also limitations. The Differential front-end demonstrated very low noise, but the threshold tuning became problematic after irradiation. Moreover, a saturation in the preamplifier feedback loop affected the return of the signal to baseline and thus increased the dead time. The Synchronous front-end showed very good timing performance, but also higher noise. For the Linear front-end all of the parameters were within specification, although this design had the largest time walk. This limitation was addressed and mitigated in an improved design. The analysis of the advantages and disadvantages of the three front-ends in the context of the CMS Inner Tracker operation requirements led to the selection of the improved design Linear front-end for integration in the final CMS readout chip., Journal of Instrumentation, 16 (12), ISSN:1748-0221

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall. A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL$\leq$1.3 LSB, an INL$\leq$2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.

This work presents the 8-channel FastIC ASIC developed in CMOS 65 nm technology suitable for the readout of positive and negative polarity sensors in high energy physics experiments, Cherenkov detectors and time-of-flight systems. The front-end can be configured to perform analog summation of up to 4 single-ended channels before discrimination in view of improving time resolution when segmenting a SiPM. The outputs encode the time-of-arrival information and linear energy measurement which captures the peak amplitude of the input signal in the 5 µA–25 mA input peak current range. Power consumption of the ASIC is 12 mW/ch with default settings. Measurements of single photon time resolution with a red-light laser source and a HPK SiPM S13360-3050CS are ≈140 ps FWHM.

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology., Comment: 7 pages, 7 figures

The recent advances in SiPM technology and the high demanding performance required by the current applications, especially in the field of time-of-flight estimation, call for a new approach in the design of the front-end amplifier to preserve the correct timing of the signals. Currently, SiPM manufacturers are offering devices with dedicated pins for fast-time outputs and recommending front-end amplifiers based on commercial devices for microwave and radio-frequency. We present in this paper our experience in designing customized wide-band amplifier front-ends for SiPM signals in high-resolution timing applications. The design consists of two stages, the first based on a low noise device (typically a JFET/MOSFET, but we have tried heterojunction transistors as well) to achieve the minimum noise figure and the second based on a MMIC used as a gain stage to boost the signal and maximize the power transfer to the output. The design procedure relies on a combination of the traditional approach of circuit simulation integrated with techniques involving the use of S-parameters, typical of RF applications. Two versions of the amplifier have been laid out and assembled and are currently under test. We present the preliminary characterization results, which demonstrates the effectiveness of the proposed design approach.

Two new radiation-hard DCDC converters are in development, which tolerate a higher input voltage (up to 48 V) and provide a larger output power compared to existing solutions. They are called bPOL48V and rPOL48V, and they employ gallium nitride devices. bPOL48V can provide 10 A of output current with better than 90% efficiency and is close to production readiness, while rPOL48V is in an early stage of development and is designed to provide larger output current with better power density. A linear regulator called linPOL48V, able step down the voltage from up to 48 V with maximum output current of 200 mA has also been designed and tested.

Agradecimentos: This work is supported by the Brazilian Ministry of Science, Technology, Innovation and Communications (MCTIC), FINEP, CNPq and FAPERJ. We also thank the staff of Eletrobrás Eletronuclear, the nuclear power plant operator. This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) — Finance Code 001. This research used the computing resources and assistance of the John David Rogers Computing Center (CCJDR) in the Institute of Physics "Gleb Wataghin", University of Campinas. The Neutrinos Angra Collaboration would like to thank the invaluable contribution of Ademarlaudo França Barbosa, who passed away, whose work has been decisive for the results presented in this article Abstract: The Neutrinos Angra Experiment has completed a major step by finishing the commissioning of the detector and the data acquisition system at the experimental site located in the Angra dos Reis nuclear power plant. The experiment, consisting of a water-based detector and associated electronics, was designed with the goal of detecting the electron antineutrinos produced by the nuclear reactor. The detection is possible due to the Inverse Beta Decay, where the final products in the water are photons in the UV-to-visible range of the spectrum. The assembled detector comprises three active volumes filled with water: (i) a cubic detector (Target) for electron antineutrinos, covered by 32 8-inch photomultiplier tubes (PMTs), (ii) a lateral layer surrounding the Target (Lateral veto) equipped with 4 PMTs and (iii) a third volume covering the top of both (Top veto), also equipped with 4 PMTs. In the present document the main features of the detector assembly as well as the integration of the readout electronics on-site are reported. Finally, some operational characteristics are shown based on analysis of the first measurements performed with the fully working detector FINANCIADORA DE ESTUDOS E PROJETOS - FINEP CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO - CNPQ FUNDAÇÃO CARLOS CHAGAS FILHO DE AMPARO À PESQUISA DO ESTADO DO RIO DE JANEIRO - FAPERJ COORDENAÇÃO DE APERFEIÇOAMENTO DE PESSOAL DE NÍVEL SUPERIOR - CAPES Fechado

Microwave SQUID (Superconducting QUantum Interference Device) multiplexing is a suitable technique for reading a large number of detector channels, using only a few connecting lines. In the HOLMESexperiment, this is based on inductively coupled rf-SQUIDs fed by TES (Transition Edge Sensors). Operation of the whole rf-SQUID chain is achieved with a single transmission line, by means of the recently introduced flux-ramp modulation technique&mdash, a sawtooth signal which allows signal reconstruction while operating the rf-SQUIDs in an open loop condition. Due to the crucial role of the sawtooth signal, it is very important that it does not suffer from ground-loop disturbances and electromagnetic interference (EMI). Introducing a transformer between the sawtooth source and the SQUID is very effective in suppressing disturbances. The sawtooth signal has both slow and fast components, and the frequency can vary between a few kHz up to a MHz, depending on the TES signal and SQUID characteristics. A transformer able to handle such a broad range of conditions must have very stringent characteristics and needs to be custom designed. Our solution exploits standard commercial and inexpensive transformers for LAN networks, stacked in a user-selectable number, to better fit the bandwidth requirements. A model that allows handling of the low- and high-frequency operating range has been developed.

Front-end electronics plays an essential role in drift chambers for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the arriving times of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. A high performance front-end electronics, characterized by low distortion, low noise and a wide bandwidth has been developed with the purpose to implement cluster timing techniques in the new drift chamber for the upgrade of the MEG experiment at Paul Sherrer Institut (CH)

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize them, retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy., Comment: 11 pages, 14 figures

In the context of the studies of the ATLAS High Luminosity LHC programme, radiation tolerant pixel detectors in CMOS technologies are investigated. To evaluate the effects of substrate resistivity on CMOS sensor performance, the H35DEMO demonstrator, containing different diode and amplifier designs, was produced in ams H35 HV-CMOS technology using four different substrate resistivities spanning from 80-1000 ohm cm-1. A glueing process using a high-precision flip-chip machine was developed in order to capacitively couple the sensors to FE-I4 Readout ASIC using a thin layer of epoxy glue with good uniformity over a large surface. The resulting assemblies were measured in beam test at the Fermilab Test Beam Facilities with 120 GeV protons and CERN SPS H8 beamline using 180 GeV pions. The in-time efficiency and tracking properties measured for the different sensor types are shown to be compatible with the ATLAS ITk requirements for its pixel sensors. In the context of the studies of the ATLAS High Luminosity LHC programme, radiation tolerant pixel detectors in CMOS technologies are investigated. To evaluate the effects of substrate resistivity on CMOS sensor performance, the H35DEMO demonstrator, containing different diode and amplifier designs, was produced in ams H35 HV-CMOS technology using four different substrate resistivities spanning from $\mathrm{80}$ to $\mathrm{1000~\Omega \cdot cm}$. A glueing process using a high-precision flip-chip machine was developed in order to capacitively couple the sensors to FE-I4 Readout ASIC using a thin layer of epoxy glue with good uniformity over a large surface. The resulting assemblies were measured in beam test at the Fermilab Test Beam Facilities with 120 GeV protons and CERN SPS H8 beamline using 80 GeV pions. The in-time efficiency and tracking properties measured for the different sensor types are shown to be compatible with the ATLAS ITk requirements for its pixel sensors.

This paper describes the performance of a prototype timing detector, based on 50 μm thick Ultra Fast Silicon Detector, as measured in a beam test using a 180 GeV/c momentum pion beam. The dependence of the time precision on the pixel capacitance and bias voltage is investigated in this paper. A timing precision from 30 ps to 100 ps (RMS), depending on the pixel capacitance, has been measured at a bias voltage of 180 V. This paper describes the performance of a prototype timing detector, based on 50 micrometer thick Ultra Fast Silicon Detector, as measured in a beam test using a 180 GeV/c momentum pion beam. The dependence of the time precision on the pixel capacitance and the bias voltage is investigated here. A timing precision from 30 ps to 100 ps, depending on the pixel capacitance, has been measured at a bias voltage of 180 V. Timing precision has also been measured as a function of the bias voltage.

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip FUNDAÇÃO DE AMPARO À PESQUISA DO ESTADO DE SÃO PAULO - FAPESP CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO - CNPQ Fechado

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e− and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

International audience; CMOS monolithic pixel detector technology is one of the options considered for the outer layer of an upgraded ATLAS pixel detector in 2026. In this upgrade pixel detector modules will be powered in series by a constant current source to reduce power losses and material budget. On-chip shunt regulators generate the local 1.8 V supply voltage from the input current to provide power to the integrated circuits. The sensor bias for monolithic sensors is often limited and not sufficiently large to allow a common bias for all sensors in the serial powering chain. In this paper, we give an introduction to the serial powering strategy for CMOS detectors with emphasis on the design and simulation results of a regulated charge pump circuit for sensor biasing. Two prototypes operating with a pumping frequency of 640 MHz, one with 6-stages and one with 19-stages, were designed and fabricated in a modified TowerJazz 0.18 μm CMOS imaging technology to provide negative bias down to − 6 V and − 20 V, respectively. Simulation results demonstrate good performance of the charge pump circuit which could be used to bias the CMOS sensor.

A versatile and reconfigurable ASIC is presented, which implements two different concepts of low level trigger (L0) for Cherenkov telescopes: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analogue clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger concepts. Each differential pair output of the discriminator is also available as a LVDS output. Differential circuitry using local feedback allows the ASIC to achieve high speed (500 MHz) while maintaining good linearity in a 1 Vpp range. Experimental results are presented. A number of prototype camera designs of the Cherenkov Telescope Array (CTA) project will use this ASIC., Accepted by JInst

Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The paper thoroughly discusses the results, mainly focused on the charge sensitive amplifier, coming from the characterization of the submitted test structures.

International audience; The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well.

International audience; FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

In this work the design of a constant fraction discriminator (CFD) to be used in the VFAT3 chip for the read-out of the triple-GEM detectors of the CMS experiment, is described. A prototype chip containing 8 CFDs was implemented using 130 nm CMOS technology and test results are shown., 0, SCOPUS: ar.j, info:eu-repo/semantics/published

This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. This upgrade calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. In this paper, we present the design and test results of a single channel 16:1 serializer and the design of a double-channel 16:1 serializer. Both designs are based on a commercial 0.25 μm silicon-on-sapphire CMOS technology. The single channel serializer consists of a serializing unit, a PLL clock generator and a line driver implemented in current mode logic (CML). The serializing unit multiplexes 16 bit parallel LVDS data into 1-bit width serial CMOS data. The serializing unit is composed of a cascade of 2:1 multiplexing circuits based on static D-flip-flops. The total jitter is measured to be 62 ps at bit error rate (BER) of 10^-12 at 5 Gbps. Random and deterministic jitters are measured to be 2.6 ps and 33.4 ps, respectively. The serializer can work from 4.0 to 5.7 Gbps with BER less than 10^-12. The power consumption is measured to be 463 mW at 5 Gbps. A proton beam test proves that the serializer meets the radiation tolerant requirements of ATLAS. A double-channel 16:1 serializer is currently under development. A low jitter LC tank PLL is shared by two serializing units to save the power consumption. The critical high speed components, including clock buffer, divider and the last stage of 2:1 multiplexing unit, are implemented with current mode logic. The post-layout simulation results of these components indicate that 8 Gbps per channel is achievable.