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A 12-bit superconductive digital filter to be used in an analog-to-digital (A/D) converter with sampling speed of 16 GHz has been designed. The filter uses modified variable threshold logic (MVTL) gates and 584 Josephson junctions but consumers only 1 mW of power. The filter receives data from an oversampling A/D modulator and processes it in real time. The filter is tested in a new XOR gate in the MVTL family. Crosstalk of AC power lines to signals is suppressed by this new design.

Based on a highly accurate current divider using switched-current technique without the need of well-matched components, a current reference generator (CRG) circuit is developed to generate and hold the weighed currents used in the data converters. This paper also presents a methodology for designing high-performance CMOS CRG circuits for low-power applications and their performance analysis for estimating the accuracy, speed, and power consumption. To demonstrate the design procedure and performance analysis, several design examples are given. The simulation results show that, for a 6-bit CRG circuit, its calibration time and holding time are 27 and 242 [[micro]seconds], respectively, and for a 8-bit CRG circuit, they are 48 and 236 [[micro]seconds], respectively. The circuit consumes 1.8 mW and achieves better than 10-bit accuracy, where a MOSIS SCNA20 2-[[micro]meter] process and a 3.3-V supply voltage are employed. Thus, the developed CRG circuit is well suited for low-power/low-voltage and moderate resolution data converters.

A high performance VMEbus interface module for NIM ADC's has been developed. Data pipelining and data suppression speed up the data acquisition. An event synchronization module for coincidence experiments has also been designed.