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This paper presents a virtual comparative study between the Analog to Digital Conversion (ADC) based Duty Cycle Modulation (DCM) and Sigma-Delta (Ʃ∆) modulation. Indeed, the Ʃ∆ modulation is the most used oversampling technique to carry out analog to digital conversion up to now. Despite of its good performances, its hardware and software implementation remains rather complex and makes its development cost rather high. To overcome this weaknesses, the new oversampling technique, duty cycle modulation, makes it possible to have better performances with very simple hardware and software structure. Thus a first order Ʃ∆ modulator is compared with a duty cycle modulator at the same central frequency of modulation in virtual simulation in terms of analog circuit, demodulation technique and the dynamic characteristics of the converters. The simulation is carried out under Matlab/Simulink R2020a with modulators at the maximum frequency of 250KHz.The dynamic performances of converters under an analog modulating signal of 1KHz reveal a) for DCM technique: SNR=45.77dB, THD=0.05055% and ENOB=7.24 bits; b) for Ʃ∆ technique: SNR=38.86dB, THD=1.574% and ENOB=6.16 bits. These results present best performances of DCM technique compared to the Ʃ∆ technique in the simulation of analog to digital conversion.

In order to meet the measurement demand of direct current in the application of industrial power system, and overcome the problems of insufficient measurement accuracy and narrow measurement range of traditional electrical signals, a high precision DC energy meter test system was designed. Field program gate way(FPGA) was used as the hardware control center, and the sampling circuit was composed of zero flux sensor, precision sampling resistor, high-precision ADC, etc. A large amount of high-speed data was collected and processed, and finally the power and electric energy test values were characterized in the form of electric energy pulse output, so as to achieve the measurement and calibration of DC parameters. The experimental results show that the test range of DC voltage and current of the system reaches 0 ~1 000 V and 0 ~200 A respectively, within the test range, it can meet the accuracy requirements of 0. 02 level of electric energy measurement. [ABSTRACT FROM AUTHOR]

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW. [ABSTRACT FROM AUTHOR]

A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC. [ABSTRACT FROM AUTHOR]

Speech emotion reflects important information other than text content in speech signal, while traditional speech recognition often ignores the emotion of text content, so it is difficult to understand more abundant emotional content from English text. In order to change this situation and get more emotional information from English texts, it is necessary to understand English speech emotion recognition. However, at present, the research on speech emotion recognition technology in China mainly focuses on Chinese, while the research on English speech emotion recognition is relatively few. Therefore, this paper studies English speech emotion recognition. The digital processing of speech signal is based on speech recognition. The digitization of speech signal is the premise of computer processing and analysis of speech signal. The preprocessing of speech signal can also be called front-end processing. The specific steps are: sampling and quantization, pre intensity and windowing. Voice endpoint detection is based on high-order differentiation of volume and waveform. In feature extraction, open smile is selected as the tool to directly extract features, libsvm is selected to establish speech emotion recognition model, and finally an experimental environment is built to verify the design method. The experimental results show that this method can better recognize the emotion of English speech and realize a high degree of human–computer interaction. [ABSTRACT FROM AUTHOR]

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

Frequency domain optical spectroscopy in the diffusive regime is currently being investigated for biomedical applications including tumor detection, therapy monitoring, exercise metabolism, and others. Analog homodyne or heterodyne detection of sinusoidally modulated signals have been the predominant method for measuring phase and amplitude of photon density waves that have traversed through tissue. Here we demonstrate the feasibility of utilizing direct digital sampling of modulated signals using a 3.6 Gigasample/second 12 bit Analog to Digital Converter. Digitally synthesized modulated signals between 50MHz and 400MHz were measured on tissue simulating phantoms at six near-infrared wavelengths. An amplitude and phase precision of 1% and 0.6 degrees were achieved during drift tests. Amplitude, phase, scattering and absorption values were compared with a well-characterized network analyzer based diffuse optical device. Measured optical properties measured with both systems were within 3.6% for absorption and 2.8% for scattering over a range of biologically relevant values. Direct digital sampling represents a viable method for frequency domain diffuse optical spectroscopy and has the potential to reduce system complexity, size, and cost.

The continuous-time pipelined(CTP) ADC is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit. It presents a resistive input impedance making it easy to drive, and places relaxed requirements on amplifiers used in the ADC. The CTP ADC attempts to address many of the challenges of discrete-time pipelined analog-to-digital conversion. This brief is a first-principles introduction to this recent architecture. [ABSTRACT FROM AUTHOR]

We consider the recovery of a continuous-time Wiener process from a quantized or a lossy compressed version of its uniform samples under limited bitrate and sampling rate. We derive a closed-form expression for the optimal tradeoff among sampling rate, bitrate, and quadratic distortion in this setting. This expression is given in terms of a reverse waterfilling formula over the asymptotic spectral distribution of a sequence of finite-rank operators associated with the optimal estimator of the Wiener process from its samples. We show that the ratio between this expression and the standard distortion rate function of the Wiener process, describing the optimal tradeoff between bitrate and distortion without a sampling constraint, is only a function of the number of bits per sample. We also consider a sub-optimal lossy compression scheme in which the continuous-time process is estimated from the output of an encoder that is optimal with respect to the discrete-time samples. We show that the latter is strictly greater than the distortion under optimal encoding but only by at most 3%. We, therefore, conclude that near optimal performance is attained even if the encoder is unaware of the continuous-time origin of the samples. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Photonic time stretch significantly extends the effective bandwidth of existing analog-to-digital convertors by slowing down the input high-speed RF signals. Non-uniform photonic time stretch further enables time bandwidth product reduction in RF signal detection by selectively stretching high-frequency features more. However, it requires the prior knowledge of spectral-temporal distribution of the input RF signal and has to reconfigure the time stretch filter for different RF input signals. Here we propose for the first time an adaptive non-uniform photonic time stretch method based on microwave photonics pre-stretching that achieves blind detection of high-speed RF signals with reduced time bandwidth product. Non-uniform photonic time stretch using both quadratic and cubic group delay response has been demonstrated and time bandwidth product compression ratios of 72% and 56% have been achieved respectively. [ABSTRACT FROM AUTHOR]

An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit but also reduces the overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier consumes only 48 nW and the adaptive-reset comparator generates a chaotic map with only 6-nW consumption. The proposed TRNG core occupies 0.0045 mm2 in 0.18- \mu \textm CMOS technology and consumes 82 nW at 270-kbps throughput with 0.6-V supply. It successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure-of-merit of 0.3 pJ/bit. [ABSTRACT FROM AUTHOR]

Bridging the gap between designed and implemented model-based controllers is a major challenge in the design cycle of industrial controllers. This gap is created due to (i) digital implementation of controller software that introduces sampling and quantization uncertainties, and (ii) uncertainties in the modeled plant's dynamics. In this paper, a new adaptive and robust model-based control approach is developed based on a nonlinear discrete sliding mode controller (DSMC) formulation to mitigate implementation imprecisions and model uncertainties, that consequently minimizes the gap between designed and implemented controllers. The new control approach incorporates the predicted values of the implementation uncertainties into the controller structure. Moreover, a generic adaptation mechanism will be derived to remove the errors in the nonlinear modeled dynamics. The proposed control approach is illustrated on a nonlinear automotive engine control problem. The designed DSMC is tested in real-time in a processor-in-the-loop (PIL) setup using an actual electronic control unit (ECU). The verification test results show that the proposed controller design, under ADC and model uncertainties, can improve the tracking performance up to 60% compared to a conventional controller design. [ABSTRACT FROM AUTHOR]

Fully digitized 2D ultrasound transducer arrays require one ADC per channel with a beamforming architecture consuming low power. We give design considerations for per-channel digitization and beamforming, and present the design and measurements of a continuous time delta-sigma modulator (CTDSM) for cardiac ultrasound applications. By integrating a mixer into the modulator frontend, the phase and frequency of the input signal can be shifted, thereby enabling both improved conversion efficiency and narrowband beamforming. To minimize the power consumption, we propose an optimization methodology using a simulated annealing framework combined with a C++ simulator solving linear electrical networks. The 3rd order single-bit feedback type modulator, implemented in a 65 nm CMOS process, achieves an SNR/SNDR of 67.8/67.4 dB across 1 MHz bandwidth consuming 131 \mu\textW of power. The achieved figure of merit of 34.2 fJ/step is comparable with state-of-the-art feedforward type multi-bit designs. We further demonstrate the influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences. [ABSTRACT FROM PUBLISHER]

In order to meet the requirements of the measurement to constant current source for high quality， a high-precision adjustable digital controlled constant current source is designed and implemented based on a single chip microcomputer in the paper. The source bases on voltage controlled constant current source circuit with series electric circuit negative feedback and uses AT89S52 single chip microcomputer as controlling key to realize the digital control. In the digital controlling part，it uses the eight-bite D/A converter DAC0832 to adjust the output current of voltage controlled constant current source and adopts high precision A/D ADC0804 converter to detect and feed back the output current，and quickly approaches to the required current by program design. Current output setting device uses the independent keyboard with the way of step by step to better digital control. In order to achieve better human-computer interaction and low power consumption，the LCD1602 liquid crystal display is applied to show the designed current and actual output current. It is implicated by the experiments that this digital controlled constant current source is highly valuable in practice for its many priorities of small ripples，high-precision，strong stability as well as simple operation，lower price and strong expansion. [ABSTRACT FROM AUTHOR]

The goal of this paper is to present the state-space approach used to obtain the digital filter directly from the netlist of the active analog filter. To reach this goal, the state-space approach has been used to obtain the state-space description of the active analog filter. Then the bilinear transformation was recalled to convert from analog domain to the digital domain. The entire approach is available software and the experimental results shown in this work have been obtained using this computer application. [ABSTRACT FROM AUTHOR]

In this paper, a digital vector impedance half-bridge meter based on virtual instruments is designed, implemented and tested. Here, not only the accuracy of the magnitude of the impedance is considered but, more importantly, its phase measurement accuracy. The meter utilizes a four-voltmeter method which is a basic modification of the well-known three-voltmeter method. The half-bridge is constructed with commercially available data acquisition (DAQ) board in the form of peripheral control interconnect cards incorporated in personal computers. The DAQ board is used only to acquire the voltages instead of using four separate voltmeters, while the excitation signal is produced by an integrated circuit signal generator. The main error in this method arises from the error in measuring the voltage values. Since the resolution of the DAQ board used here is 16 bits; expect that absolute errors due to A/D conversion will be around 0.305 mV for ±10 V range. Detailed error analysis of the method is included in the context of the paper. It is found that the errors in the impedance magnitude is fairly small and relatively less sensitive on the resolution of the voltmeters because of the relative measurements in the half bridge with a precise reference resistance. The original three voltmeter vector impedance meter has relatively large error in the phase especially in the small phase angles. To decrease the phase error to an acceptable range, one has to increase the resolution of the voltmeter appreciably, which makes them expensive. The other solution to reduce the error in the phase angle with less cost is to add a fourth voltmeter which acquires directly the small phase angles. In this case, it is found that, a much lower resolution voltmeter can be utilized while achieving an acceptable measurement accuracy of the impedance. [ABSTRACT FROM AUTHOR]

Due to technology scaling, the design of the conventional-type analog-to-digital converter (ADC), which uses an operational amplifier as one of its building blocks, becomes more difficult. In this brief, new techniques to design time-based ADC (TADC), which uses a voltage-controlled oscillator (VCO), are proposed. The VCO is followed by a time-to-digital converter, implemented in a $\Sigma\Delta$ architecture. A novel architecture, using a multibit, nonlinear internal quantizer and a feedback digital-to-time converter, implemented by using phase interpolation, is employed to compensate the nonlinear transfer curve of the VCO. Dynamic element matching and calibration are used to improve the robustness of the TADC against mismatch. The TADC uses an implicit sample and hold that relaxes the bounds on input frequency. A TADC implemented in 0.13- \mu\mbox{m} CMOS technology achieves a measured signal-to-noise + distortion ratio of 60.2 dB and a dynamic range of 11 b for a bandwidth of 2 MHz. [ABSTRACT FROM AUTHOR]

A weighted mean square error (WMSE) approach to optimising digital filters is delineated. It is applied in the current work to optimising the classical Al‐Alaoui IIR differentiators to obtain new improved wideband differentiators of varying orders. These can be directly used for analog to digital conversion and in many digital signal processing applications. The weighted MSE approach is motivated by the Al‐Alaoui WMSE approach to pattern recognition. In addition, the differentiators are converted to integrators of similar orders that are further optimised. Various examples and comparisons are presented to demonstrate the viability of the proposed approach. [ABSTRACT FROM AUTHOR]

Copyright of Automatika: Journal for Control, Measurement, Electronics, Computing & Communications is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)